Re: [U-Boot] [PATCH 08/10] odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412

2014-06-11 Thread Przemyslaw Marczak 

Hello Inha,
On 06/11/2014 03:33 AM, Inha Song wrote:

Hi Przemyslaw,

In U3 board, cooling pan is not work.
I think, cooling pan setting is need in board_gpio_init().
(X2 board use cooling pan pwr form USB port)

best regards,
Inha Song.


Thank you for testing. I have a board without the cooling fan,
but this is a right notice - this feature should be included for this 
board - and come with next patch set.


regards,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH 08/10] odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412

2014-06-10 Thread Inha Song 
Hi Przemyslaw,

In U3 board, cooling pan is not work.
I think, cooling pan setting is need in board_gpio_init().
(X2 board use cooling pan pwr form USB port)

best regards,
Inha Song.

On Tue, 10 Jun 2014 13:33:02 +0200
Przemyslaw Marczak  wrote:

> This board file supports standard features of Odroid X2 and U3 boards:
> - Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 
> 800MHz,
> - MAX77686 power regulator,
> - USB PHY,
> - enable XCL205 - power for board peripherials
> - check board type: U3 or X2.
> 
> Signed-off-by: Przemyslaw Marczak 
> Cc: Minkyu Kang 
> Cc: Tom Rini 
> ---
>  board/samsung/odroid/Makefile |   8 +
>  board/samsung/odroid/odroid.c | 432 
> ++
>  board/samsung/odroid/setup.h  | 227 ++
>  3 files changed, 667 insertions(+)
>  create mode 100644 board/samsung/odroid/Makefile
>  create mode 100644 board/samsung/odroid/odroid.c
>  create mode 100644 board/samsung/odroid/setup.h
> 
> diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
> new file mode 100644
> index 000..b98aaeb
> --- /dev/null
> +++ b/board/samsung/odroid/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
> +# Przemyslaw Marczak 
> +#
> +# SPDX-License-Identifier:   GPL-2.0+
> +#
> +
> +obj-y:= odroid.o
> diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
> new file mode 100644
> index 000..20a41b2
> --- /dev/null
> +++ b/board/samsung/odroid/odroid.c
> @@ -0,0 +1,432 @@
> +/*
> + * Copyright (C) 2014 Samsung Electronics
> + * Przemyslaw Marczak 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "setup.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* Odroid board types */
> +enum {
> + ODROID_TYPE_U3,
> + ODROID_TYPE_X2,
> +};
> +
> +static void set_board_type(void)
> +{
> + int val;
> +
> + /* Check GPC1 pin 2 */
> + gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
> + gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
> + gpio_direction_input(EXYNOS4X12_GPIO_C12);
> +
> + /* XCL205 - needs some latch time */
> + mdelay(10);
> +
> + /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
> + val = gpio_get_value(EXYNOS4X12_GPIO_C12);
> + if (val)
> + gd->board_type = ODROID_TYPE_X2;
> + else
> + gd->board_type = ODROID_TYPE_U3;
> +}
> +
> +const char *get_board_type(void)
> +{
> + const char *board_type_str[] = {"U3", "X2"};
> +
> + set_board_type();
> +
> + return board_type_str[gd->board_type];
> +}
> +
> +const char *get_board_type_fdt(void)
> +{
> + const char *board_type_fdt[] = {"u3", "x2"};
> +
> + return board_type_fdt[gd->board_type];
> +}
> +
> +static void board_clock_init(void)
> +{
> + unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
> + struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
> + samsung_get_base_clock();
> +
> + /*
> +  * CMU_CPU clocks src to MPLL
> +  * Bit values: 0  ; 1
> +  * MUX_APLL_SEL:FIN_PLL   ; FOUT_APLL
> +  * MUX_CORE_SEL:MOUT_APLL ; SCLK_MPLL
> +  * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
> +  * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
> + */
> + clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) |
> +   MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1);
> + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
> +   MUX_MPLL_USER_SEL_C(1);
> +
> + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> +
> + /* Wait for mux change */
> + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
> + continue;
> +
> + /* Set APLL to 1000MHz */
> + clr_pll_con0 = SDIV(0x7) | PDIV(0x3f) | MDIV(0x3ff) | FSEL(0x1);
> + set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
> +
> + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
> +
> + /* Wait for PLL to be locked */
> + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
> + continue;
> +
> + /* Set CMU_CPU clocks src to APLL */
> + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
> +   MUX_MPLL_USER_SEL_C(1);
> + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> +
> + /* Wait for mux change */
> + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
> + continue;
> +
> + set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
> +   PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
> +   APLL_RATIO(0) | CORE2_RATIO(0);
> + /*
> +  * Set dividers for MOUTcore = 1000 MHz
> +  * coreout =  MOUT / (ratio + 1) = 1000 MHz (0)
> +  * corem0 =

[U-Boot] [PATCH 08/10] odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412

2014-06-10 Thread Przemyslaw Marczak 
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable XCL205 - power for board peripherials
- check board type: U3 or X2.

Signed-off-by: Przemyslaw Marczak 
Cc: Minkyu Kang 
Cc: Tom Rini 
---
 board/samsung/odroid/Makefile |   8 +
 board/samsung/odroid/odroid.c | 432 ++
 board/samsung/odroid/setup.h  | 227 ++
 3 files changed, 667 insertions(+)
 create mode 100644 board/samsung/odroid/Makefile
 create mode 100644 board/samsung/odroid/odroid.c
 create mode 100644 board/samsung/odroid/setup.h

diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
new file mode 100644
index 000..b98aaeb
--- /dev/null
+++ b/board/samsung/odroid/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
+# Przemyslaw Marczak 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := odroid.o
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
new file mode 100644
index 000..20a41b2
--- /dev/null
+++ b/board/samsung/odroid/odroid.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "setup.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Odroid board types */
+enum {
+   ODROID_TYPE_U3,
+   ODROID_TYPE_X2,
+};
+
+static void set_board_type(void)
+{
+   int val;
+
+   /* Check GPC1 pin 2 */
+   gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
+   gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
+   gpio_direction_input(EXYNOS4X12_GPIO_C12);
+
+   /* XCL205 - needs some latch time */
+   mdelay(10);
+
+   /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
+   val = gpio_get_value(EXYNOS4X12_GPIO_C12);
+   if (val)
+   gd->board_type = ODROID_TYPE_X2;
+   else
+   gd->board_type = ODROID_TYPE_U3;
+}
+
+const char *get_board_type(void)
+{
+   const char *board_type_str[] = {"U3", "X2"};
+
+   set_board_type();
+
+   return board_type_str[gd->board_type];
+}
+
+const char *get_board_type_fdt(void)
+{
+   const char *board_type_fdt[] = {"u3", "x2"};
+
+   return board_type_fdt[gd->board_type];
+}
+
+static void board_clock_init(void)
+{
+   unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+   struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+   samsung_get_base_clock();
+
+   /*
+* CMU_CPU clocks src to MPLL
+* Bit values: 0  ; 1
+* MUX_APLL_SEL:FIN_PLL   ; FOUT_APLL
+* MUX_CORE_SEL:MOUT_APLL ; SCLK_MPLL
+* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
+* MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
+   */
+   clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) |
+ MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1);
+   set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
+ MUX_MPLL_USER_SEL_C(1);
+
+   clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+   /* Wait for mux change */
+   while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+   continue;
+
+   /* Set APLL to 1000MHz */
+   clr_pll_con0 = SDIV(0x7) | PDIV(0x3f) | MDIV(0x3ff) | FSEL(0x1);
+   set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
+
+   clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
+
+   /* Wait for PLL to be locked */
+   while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
+   continue;
+
+   /* Set CMU_CPU clocks src to APLL */
+   set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
+ MUX_MPLL_USER_SEL_C(1);
+   clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+   /* Wait for mux change */
+   while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+   continue;
+
+   set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
+ PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
+ APLL_RATIO(0) | CORE2_RATIO(0);
+   /*
+* Set dividers for MOUTcore = 1000 MHz
+* coreout =  MOUT / (ratio + 1) = 1000 MHz (0)
+* corem0 = armclk / (ratio + 1) = 333 MHz (2)
+* corem1 = armclk / (ratio + 1) = 166 MHz (5)
+* periph = armclk / (ratio + 1) = 1000 MHz (0)
+* atbout =   MOUT / (ratio + 1) = 200 MHz (4)
+* pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
+* sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
+* core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
+   */
+   clr = CORE_RATIO(0x7)