Re: [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file

[Enric Balletbo Serra]

2017-08-19 0:02 GMT+02:00 Pau Pajuelo :
> Tested-by: Pau Pajuelo 
>
> 2017-08-17 3:06 GMT+02:00 Ladislav Michl :
>> Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
>> by moving SPL related functions into separate file.
>>
>> Signed-off-by: Ladislav Michl 
>> ---
>>  board/isee/igep00x0/Makefile   |   6 +-
>>  board/isee/igep00x0/common.c   |  80 ++
>>  board/isee/igep00x0/igep00x0.c | 128 
>> -
>>  board/isee/igep00x0/spl.c  |  64 +
>>  4 files changed, 149 insertions(+), 129 deletions(-)
>>
>> diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
>> index 68b151c3c5..74594da771 100644
>> --- a/board/isee/igep00x0/Makefile
>> +++ b/board/isee/igep00x0/Makefile
>> @@ -5,4 +5,8 @@
>>  # SPDX-License-Identifier: GPL-2.0+
>>  #
>>
>> -obj-y  := igep00x0.o
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y  := spl.o common.o
>> +else
>> +obj-y  := igep00x0.o common.o
>> +endif
>> diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
>> new file mode 100644
>> index 00..b8f1c14f6a
>> --- /dev/null
>> +++ b/board/isee/igep00x0/common.c
>> @@ -0,0 +1,80 @@
>> +/*
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include "igep00x0.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/*
>> + * Routine: set_muxconf_regs
>> + * Description: Setting up the configuration Mux registers specific to the
>> + * hardware. Many pins need to be moved from protect to primary
>> + * mode.
>> + */
>> +void set_muxconf_regs(void)
>> +{
>> +   MUX_DEFAULT();
>> +
>> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
>> +   MUX_IGEP0020();
>> +#endif
>> +
>> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
>> +   MUX_IGEP0030();
>> +#endif
>> +}
>> +
>> +/*
>> + * Routine: board_init
>> + * Description: Early hardware init.
>> + */
>> +int board_init(void)
>> +{
>> +   int loops = 100;
>> +
>> +   /* find out flash memory type, assume NAND first */
>> +   gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> +   gpmc_init();
>> +
>> +   /* Issue a RESET and then READID */
>> +   writeb(NAND_CMD_RESET, _cfg->cs[0].nand_cmd);
>> +   writeb(NAND_CMD_STATUS, _cfg->cs[0].nand_cmd);
>> +   while ((readl(_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
>> +   != NAND_STATUS_READY) {
>> +   udelay(1);
>> +   if (--loops == 0) {
>> +   gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> +   gpmc_init();/* reinitialize for OneNAND */
>> +   break;
>> +   }
>> +   }
>> +
>> +   /* boot param addr */
>> +   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
>> +
>> +#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
>> +   status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
>> +#endif
>> +
>> +   return 0;
>> +}
>> +
>> +#if defined(CONFIG_MMC)
>> +int board_mmc_init(bd_t *bis)
>> +{
>> +   return omap_mmc_init(0, 0, 0, -1, -1);
>> +}
>> +
>> +void board_mmc_power_init(void)
>> +{
>> +   twl4030_power_mmc_init(0);
>> +}
>> +#endif
>> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
>> index a7a75601dd..74f9bab093 100644
>> --- a/board/isee/igep00x0/igep00x0.c
>> +++ b/board/isee/igep00x0/igep00x0.c
>> @@ -20,15 +20,12 @@
>>  #include 
>>  #include 
>>  #include 
>> -#include 
>>  #include 
>>  #include 
>>  #include 
>>  #include 
>>  #include "igep00x0.h"
>>
>> -DECLARE_GLOBAL_DATA_PTR;
>> -
>>  static const struct ns16550_platdata igep_serial = {
>> .base = OMAP34XX_UART3,
>> .reg_shift = 2,
>> @@ -41,98 +38,6 @@ U_BOOT_DEVICE(igep_uart) = {
>> _serial
>>  };
>>
>> -/*
>> - * Routine: board_init
>> - * Description: Early hardware init.
>> - */
>> -int board_init(void)
>> -{
>> -   int loops = 100;
>> -
>> -   /* find out flash memory type, assume NAND first */
>> -   gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> -   gpmc_init();
>> -
>> -   /* Issue a RESET and then READID */
>> -   writeb(NAND_CMD_RESET, _cfg->cs[0].nand_cmd);
>> -   writeb(NAND_CMD_STATUS, _cfg->cs[0].nand_cmd);
>> -   while ((readl(_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
>> -   != NAND_STATUS_READY) {
>> -   udelay(1);
>> -   if (--loops == 0) {
>> -   gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> -   gpmc_init();/* reinitialize for OneNAND */
>> -   break;
>> -   }
>> -   }
>> -
>> -   /* boot param addr */
>> -   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
>> -
>> -#if 

Re: [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file

[Pau Pajuelo]

Tested-by: Pau Pajuelo 

2017-08-17 3:06 GMT+02:00 Ladislav Michl :
> Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
> by moving SPL related functions into separate file.
>
> Signed-off-by: Ladislav Michl 
> ---
>  board/isee/igep00x0/Makefile   |   6 +-
>  board/isee/igep00x0/common.c   |  80 ++
>  board/isee/igep00x0/igep00x0.c | 128 
> -
>  board/isee/igep00x0/spl.c  |  64 +
>  4 files changed, 149 insertions(+), 129 deletions(-)
>
> diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
> index 68b151c3c5..74594da771 100644
> --- a/board/isee/igep00x0/Makefile
> +++ b/board/isee/igep00x0/Makefile
> @@ -5,4 +5,8 @@
>  # SPDX-License-Identifier: GPL-2.0+
>  #
>
> -obj-y  := igep00x0.o
> +ifdef CONFIG_SPL_BUILD
> +obj-y  := spl.o common.o
> +else
> +obj-y  := igep00x0.o common.o
> +endif
> diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
> new file mode 100644
> index 00..b8f1c14f6a
> --- /dev/null
> +++ b/board/isee/igep00x0/common.c
> @@ -0,0 +1,80 @@
> +/*
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "igep00x0.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * hardware. Many pins need to be moved from protect to primary
> + * mode.
> + */
> +void set_muxconf_regs(void)
> +{
> +   MUX_DEFAULT();
> +
> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
> +   MUX_IGEP0020();
> +#endif
> +
> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
> +   MUX_IGEP0030();
> +#endif
> +}
> +
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> +   int loops = 100;
> +
> +   /* find out flash memory type, assume NAND first */
> +   gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
> +   gpmc_init();
> +
> +   /* Issue a RESET and then READID */
> +   writeb(NAND_CMD_RESET, _cfg->cs[0].nand_cmd);
> +   writeb(NAND_CMD_STATUS, _cfg->cs[0].nand_cmd);
> +   while ((readl(_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
> +   != NAND_STATUS_READY) {
> +   udelay(1);
> +   if (--loops == 0) {
> +   gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
> +   gpmc_init();/* reinitialize for OneNAND */
> +   break;
> +   }
> +   }
> +
> +   /* boot param addr */
> +   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> +#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
> +   status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
> +#endif
> +
> +   return 0;
> +}
> +
> +#if defined(CONFIG_MMC)
> +int board_mmc_init(bd_t *bis)
> +{
> +   return omap_mmc_init(0, 0, 0, -1, -1);
> +}
> +
> +void board_mmc_power_init(void)
> +{
> +   twl4030_power_mmc_init(0);
> +}
> +#endif
> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
> index a7a75601dd..74f9bab093 100644
> --- a/board/isee/igep00x0/igep00x0.c
> +++ b/board/isee/igep00x0/igep00x0.c
> @@ -20,15 +20,12 @@
>  #include 
>  #include 
>  #include 
> -#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include "igep00x0.h"
>
> -DECLARE_GLOBAL_DATA_PTR;
> -
>  static const struct ns16550_platdata igep_serial = {
> .base = OMAP34XX_UART3,
> .reg_shift = 2,
> @@ -41,98 +38,6 @@ U_BOOT_DEVICE(igep_uart) = {
> _serial
>  };
>
> -/*
> - * Routine: board_init
> - * Description: Early hardware init.
> - */
> -int board_init(void)
> -{
> -   int loops = 100;
> -
> -   /* find out flash memory type, assume NAND first */
> -   gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
> -   gpmc_init();
> -
> -   /* Issue a RESET and then READID */
> -   writeb(NAND_CMD_RESET, _cfg->cs[0].nand_cmd);
> -   writeb(NAND_CMD_STATUS, _cfg->cs[0].nand_cmd);
> -   while ((readl(_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
> -   != NAND_STATUS_READY) {
> -   udelay(1);
> -   if (--loops == 0) {
> -   gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
> -   gpmc_init();/* reinitialize for OneNAND */
> -   break;
> -   }
> -   }
> -
> -   /* boot param addr */
> -   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> -
> -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
> -   status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
> -#endif
> -
> -   return 0;
> -}
> -
> -#ifdef CONFIG_SPL_BUILD
> -/*
> - * Routine: 

[U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file

[Ladislav Michl]

Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
by moving SPL related functions into separate file.

Signed-off-by: Ladislav Michl 
---
 board/isee/igep00x0/Makefile   |   6 +-
 board/isee/igep00x0/common.c   |  80 ++
 board/isee/igep00x0/igep00x0.c | 128 -
 board/isee/igep00x0/spl.c  |  64 +
 4 files changed, 149 insertions(+), 129 deletions(-)

diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
index 68b151c3c5..74594da771 100644
--- a/board/isee/igep00x0/Makefile
+++ b/board/isee/igep00x0/Makefile
@@ -5,4 +5,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y  := igep00x0.o
+ifdef CONFIG_SPL_BUILD
+obj-y  := spl.o common.o
+else
+obj-y  := igep00x0.o common.o
+endif
diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
new file mode 100644
index 00..b8f1c14f6a
--- /dev/null
+++ b/board/isee/igep00x0/common.c
@@ -0,0 +1,80 @@
+/*
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "igep00x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+   MUX_DEFAULT();
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+   MUX_IGEP0020();
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+   MUX_IGEP0030();
+#endif
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+   int loops = 100;
+
+   /* find out flash memory type, assume NAND first */
+   gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+   gpmc_init();
+
+   /* Issue a RESET and then READID */
+   writeb(NAND_CMD_RESET, _cfg->cs[0].nand_cmd);
+   writeb(NAND_CMD_STATUS, _cfg->cs[0].nand_cmd);
+   while ((readl(_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+   != NAND_STATUS_READY) {
+   udelay(1);
+   if (--loops == 0) {
+   gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+   gpmc_init();/* reinitialize for OneNAND */
+   break;
+   }
+   }
+
+   /* boot param addr */
+   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+   status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
+#endif
+
+   return 0;
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(bd_t *bis)
+{
+   return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+   twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index a7a75601dd..74f9bab093 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -20,15 +20,12 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
 #include 
 #include "igep00x0.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static const struct ns16550_platdata igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
@@ -41,98 +38,6 @@ U_BOOT_DEVICE(igep_uart) = {
_serial
 };
 
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-   int loops = 100;
-
-   /* find out flash memory type, assume NAND first */
-   gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
-   gpmc_init();
-
-   /* Issue a RESET and then READID */
-   writeb(NAND_CMD_RESET, _cfg->cs[0].nand_cmd);
-   writeb(NAND_CMD_STATUS, _cfg->cs[0].nand_cmd);
-   while ((readl(_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
-   != NAND_STATUS_READY) {
-   udelay(1);
-   if (--loops == 0) {
-   gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
-   gpmc_init();/* reinitialize for OneNAND */
-   break;
-   }
-   }
-
-   /* boot param addr */
-   gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
-   status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
-   return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
-   int mfr, id, err = identify_nand_chip(, );
-
-   timings->mr = MICRON_V_MR_165;
-   if (!err) {
-   switch (mfr) {
-   case NAND_MFR_HYNIX:
-   timings->mcfg =