Re: [U-Boot] [PATCH 1/2] mtd: nand: tegra: convert to driver model and live tree

[Masahiro Yamada]

2018-02-24 1:40 GMT+09:00 Stefan Agner :
> On 21.02.2018 16:16, Marcel Ziswiler wrote:
>> From: Marcel Ziswiler 
>>
>> The Tegra NAND driver recently got broken by ongoing driver model resp.
>> live tree migration work:
>>
>> NAND:  Could not decode nand-flash in device tree
>> Tegra NAND init failed
>> 0 MiB
>>
>> A patch for NAND uclass support was proposed about a year ago:
>> https://patchwork.ozlabs.org/patch/722282/
>>
>> It was not merged and I do not see on-going work for this.
>>
>> This commit just provides a driver model probe hook to retrieve further
>> configuration from the live device tree. As there is no NAND ulass as of
>> yet (ab)using UCLASS_MISC. Once UCLASS_NAND is supported, it would be
>> possible to migrate to it.
>>
>> Signed-off-by: Marcel Ziswiler 
>>
>> ---



>>
>> +U_BOOT_DRIVER(tegra_nand) = {
>> + .name = "tegra-nand",
>> + .id = UCLASS_MISC,
>
> There is also UCLASS_MTD, which I was going to use in a upcoming
> patchset for mxs_nand.c.
>
> I see that drivers/mtd/nand/denali_dt.c is currently using UCLASS_MISC,
> Masahiro, any reason for that?


I do not remember why.
Maybe, I just missed UCLASS_MTD.

The denali_dt only uses .probe(), so any uclass would be fine.
I guess I chose something that sounded generic, so "MISC".




> Commit d85879938d ("dm: implement a MTD uclass") seems to suggest that
> it should be fine for NAND flash drivers too...
>
> --
> Stefan
>



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 1/2] mtd: nand: tegra: convert to driver model and live tree

[Stefan Agner]

On 21.02.2018 16:16, Marcel Ziswiler wrote:
> From: Marcel Ziswiler 
> 
> The Tegra NAND driver recently got broken by ongoing driver model resp.
> live tree migration work:
> 
> NAND:  Could not decode nand-flash in device tree
> Tegra NAND init failed
> 0 MiB
> 
> A patch for NAND uclass support was proposed about a year ago:
> https://patchwork.ozlabs.org/patch/722282/
> 
> It was not merged and I do not see on-going work for this.
> 
> This commit just provides a driver model probe hook to retrieve further
> configuration from the live device tree. As there is no NAND ulass as of
> yet (ab)using UCLASS_MISC. Once UCLASS_NAND is supported, it would be
> possible to migrate to it.
> 
> Signed-off-by: Marcel Ziswiler 
> 
> ---
> 
>  drivers/mtd/nand/tegra_nand.c | 98 
> ---
>  1 file changed, 55 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
> index c03c9cb178..405018018c 100644
> --- a/drivers/mtd/nand/tegra_nand.c
> +++ b/drivers/mtd/nand/tegra_nand.c
> @@ -18,6 +18,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include "tegra_nand.h"
>  
>  DECLARE_GLOBAL_DATA_PTR;
> @@ -29,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR;
>  /* ECC bytes to be generated for tag data */
>  #define TAG_ECC_BYTES4
>  
> +static const struct udevice_id tegra_nand_dt_ids[] = {
> + {
> + .compatible = "nvidia,tegra20-nand",
> + },
> + { /* sentinel */ }
> +};
> +
>  /* 64 byte oob block info for large page (== 2KB) device
>   *
>   * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
> @@ -91,9 +99,11 @@ struct nand_drv {
>   struct fdt_nand config;
>  };
>  
> -static struct nand_drv nand_ctrl;
> -static struct mtd_info *our_mtd;
> -static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
> +struct tegra_nand_info {
> + struct udevice *dev;
> + struct nand_drv nand_ctrl;
> + struct nand_chip nand_chip;
> +};
>  
>  /**
>   * Wait for command completion
> @@ -453,8 +463,8 @@ static void stop_command(struct nand_ctlr *reg)
>   * @param *reg_val   address of reg_val
>   * @return 0 if ok, -1 on error
>   */
> -static int set_bus_width_page_size(struct fdt_nand *config,
> - u32 *reg_val)
> +static int set_bus_width_page_size(struct mtd_info *our_mtd,
> +struct fdt_nand *config, u32 *reg_val)
>  {
>   if (config->width == 8)
>   *reg_val = CFG_BUS_WIDTH_8BIT;
> @@ -514,7 +524,7 @@ static int nand_rw_page(struct mtd_info *mtd,
> struct nand_chip *chip,
>  
>   info = (struct nand_drv *)nand_get_controller_data(chip);
>   config = >config;
> - if (set_bus_width_page_size(config, _val))
> + if (set_bus_width_page_size(mtd, config, _val))
>   return -EINVAL;
>  
>   /* Need to be 4-byte aligned */
> @@ -722,7 +732,7 @@ static int nand_rw_oob(struct mtd_info *mtd,
> struct nand_chip *chip,
>   if (((int)chip->oob_poi) & 0x03)
>   return -EINVAL;
>   info = (struct nand_drv *)nand_get_controller_data(chip);
> - if (set_bus_width_page_size(>config, _val))
> + if (set_bus_width_page_size(mtd, >config, _val))
>   return -EINVAL;
>  
>   stop_command(info->reg);
> @@ -883,51 +893,39 @@ static void setup_timing(unsigned
> timing[FDT_NAND_TIMING_COUNT],
>  /**
>   * Decode NAND parameters from the device tree
>   *
> - * @param blob   Device tree blob
> - * @param node   Node containing "nand-flash" compatible node
> + * @param devDriver model device
> + * @param config Device tree NAND configuration
>   * @return 0 if ok, -ve on error (FDT_ERR_...)
>   */
> -static int fdt_decode_nand(const void *blob, int node, struct fdt_nand 
> *config)
> +static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
>  {
>   int err;
>  
> - config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
> - config->enabled = fdtdec_get_is_enabled(blob, node);
> - config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
> - err = gpio_request_by_name_nodev(offset_to_ofnode(node),
> - "nvidia,wp-gpios", 0, >wp_gpio, GPIOD_IS_OUT);
> + config->reg = (struct nand_ctlr *)dev_read_addr(dev);
> + config->enabled = dev_read_enabled(dev);
> + config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
> + err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, >wp_gpio,
> +GPIOD_IS_OUT);
>   if (err)
>   return err;
> - err = fdtdec_get_int_array(blob, node, "nvidia,timing",
> - config->timing, FDT_NAND_TIMING_COUNT);
> + err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
> +  FDT_NAND_TIMING_COUNT);
>   if (err < 0)
>   return err;
>  
> - 

Re: [U-Boot] [PATCH 1/2] mtd: nand: tegra: convert to driver model and live tree

[Simon Glass]

On 21 February 2018 at 08:16, Marcel Ziswiler  wrote:
>
> From: Marcel Ziswiler 
>
> The Tegra NAND driver recently got broken by ongoing driver model resp.
> live tree migration work:
>
> NAND:  Could not decode nand-flash in device tree
> Tegra NAND init failed
> 0 MiB
>
> A patch for NAND uclass support was proposed about a year ago:
> https://patchwork.ozlabs.org/patch/722282/
>
> It was not merged and I do not see on-going work for this.
>
> This commit just provides a driver model probe hook to retrieve further
> configuration from the live device tree. As there is no NAND ulass as of
> yet (ab)using UCLASS_MISC. Once UCLASS_NAND is supported, it would be
> possible to migrate to it.
>
> Signed-off-by: Marcel Ziswiler 
>
> ---
>
>  drivers/mtd/nand/tegra_nand.c | 98 
> ---
>  1 file changed, 55 insertions(+), 43 deletions(-)

Reviewed-by: Simon Glass 
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[U-Boot] [PATCH 1/2] mtd: nand: tegra: convert to driver model and live tree

[Marcel Ziswiler]

From: Marcel Ziswiler 

The Tegra NAND driver recently got broken by ongoing driver model resp.
live tree migration work:

NAND:  Could not decode nand-flash in device tree
Tegra NAND init failed
0 MiB

A patch for NAND uclass support was proposed about a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

This commit just provides a driver model probe hook to retrieve further
configuration from the live device tree. As there is no NAND ulass as of
yet (ab)using UCLASS_MISC. Once UCLASS_NAND is supported, it would be
possible to migrate to it.

Signed-off-by: Marcel Ziswiler 

---

 drivers/mtd/nand/tegra_nand.c | 98 ---
 1 file changed, 55 insertions(+), 43 deletions(-)

diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index c03c9cb178..405018018c 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "tegra_nand.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -29,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR;
 /* ECC bytes to be generated for tag data */
 #define TAG_ECC_BYTES  4
 
+static const struct udevice_id tegra_nand_dt_ids[] = {
+   {
+   .compatible = "nvidia,tegra20-nand",
+   },
+   { /* sentinel */ }
+};
+
 /* 64 byte oob block info for large page (== 2KB) device
  *
  * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
@@ -91,9 +99,11 @@ struct nand_drv {
struct fdt_nand config;
 };
 
-static struct nand_drv nand_ctrl;
-static struct mtd_info *our_mtd;
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+struct tegra_nand_info {
+   struct udevice *dev;
+   struct nand_drv nand_ctrl;
+   struct nand_chip nand_chip;
+};
 
 /**
  * Wait for command completion
@@ -453,8 +463,8 @@ static void stop_command(struct nand_ctlr *reg)
  * @param *reg_val address of reg_val
  * @return 0 if ok, -1 on error
  */
-static int set_bus_width_page_size(struct fdt_nand *config,
-   u32 *reg_val)
+static int set_bus_width_page_size(struct mtd_info *our_mtd,
+  struct fdt_nand *config, u32 *reg_val)
 {
if (config->width == 8)
*reg_val = CFG_BUS_WIDTH_8BIT;
@@ -514,7 +524,7 @@ static int nand_rw_page(struct mtd_info *mtd, struct 
nand_chip *chip,
 
info = (struct nand_drv *)nand_get_controller_data(chip);
config = >config;
-   if (set_bus_width_page_size(config, _val))
+   if (set_bus_width_page_size(mtd, config, _val))
return -EINVAL;
 
/* Need to be 4-byte aligned */
@@ -722,7 +732,7 @@ static int nand_rw_oob(struct mtd_info *mtd, struct 
nand_chip *chip,
if (((int)chip->oob_poi) & 0x03)
return -EINVAL;
info = (struct nand_drv *)nand_get_controller_data(chip);
-   if (set_bus_width_page_size(>config, _val))
+   if (set_bus_width_page_size(mtd, >config, _val))
return -EINVAL;
 
stop_command(info->reg);
@@ -883,51 +893,39 @@ static void setup_timing(unsigned 
timing[FDT_NAND_TIMING_COUNT],
 /**
  * Decode NAND parameters from the device tree
  *
- * @param blob Device tree blob
- * @param node Node containing "nand-flash" compatible node
+ * @param dev  Driver model device
+ * @param config   Device tree NAND configuration
  * @return 0 if ok, -ve on error (FDT_ERR_...)
  */
-static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
+static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
 {
int err;
 
-   config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
-   config->enabled = fdtdec_get_is_enabled(blob, node);
-   config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
-   err = gpio_request_by_name_nodev(offset_to_ofnode(node),
-   "nvidia,wp-gpios", 0, >wp_gpio, GPIOD_IS_OUT);
+   config->reg = (struct nand_ctlr *)dev_read_addr(dev);
+   config->enabled = dev_read_enabled(dev);
+   config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
+   err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, >wp_gpio,
+  GPIOD_IS_OUT);
if (err)
return err;
-   err = fdtdec_get_int_array(blob, node, "nvidia,timing",
-   config->timing, FDT_NAND_TIMING_COUNT);
+   err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
+FDT_NAND_TIMING_COUNT);
if (err < 0)
return err;
 
-   /* Now look up the controller and decode that */
-   node = fdt_next_node(blob, node, NULL);
-   if (node < 0)
-   return node;
-
return 0;
 }
 
-/**
- * Board-specific NAND initialization
- *
- * @param nand nand