Add support for the reset controller that's used on the i.MX7D
and i.MX8MQ. This will be needed to be able to assert the PCIe
reset pins. Bindings taken from Linux, driver implementation
mostly taken from Linux and adjusted to U-Boot infrastructure.
Signed-off-by: Patrick Wildt
---
drivers/reset/Kconfig| 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx7.c | 312 +++
include/dt-bindings/reset/imx7-reset.h | 52
include/dt-bindings/reset/imx8mq-reset.h | 64 +
5 files changed, 436 insertions(+)
create mode 100644 drivers/reset/reset-imx7.c
create mode 100644 include/dt-bindings/reset/imx7-reset.h
create mode 100755 include/dt-bindings/reset/imx8mq-reset.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6ec6f39c85..976f3a701c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -127,4 +127,11 @@ config RESET_HISILICON
help
Support for reset controller on HiSilicon SoCs.
+config RESET_IMX7
+ bool "i.MX7/8 Reset Driver"
+ depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
+ default y
+ help
+ Support for reset controller on i.MX7/8 SoCs.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 7fec75bb49..f5875fce09 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
+obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
new file mode 100644
index 00..f2ca5cf801
--- /dev/null
+++ b/drivers/reset/reset-imx7.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct imx7_reset_priv {
+ void __iomem *base;
+ struct reset_ops ops;
+};
+
+struct imx7_src_signal {
+ unsigned int offset, bit;
+};
+
+enum imx7_src_registers {
+ SRC_A7RCR0 = 0x0004,
+ SRC_M4RCR = 0x000c,
+ SRC_ERCR= 0x0014,
+ SRC_HSICPHY_RCR = 0x001c,
+ SRC_USBOPHY1_RCR= 0x0020,
+ SRC_USBOPHY2_RCR= 0x0024,
+ SRC_MIPIPHY_RCR = 0x0028,
+ SRC_PCIEPHY_RCR = 0x002c,
+ SRC_DDRC_RCR= 0x1000,
+};
+
+static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
+ [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
+ [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
+ [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
+ [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
+ [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
+ [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
+ [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
+ [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
+ [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
+ [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
+ [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
+ [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
+ [IMX7_RESET_EIM_RST]= { SRC_ERCR, BIT(0) },
+ [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
+ [IMX7_RESET_USBPHY1_POR]= { SRC_USBOPHY1_RCR, BIT(0) },
+ [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
+ [IMX7_RESET_USBPHY2_POR]= { SRC_USBOPHY2_RCR, BIT(0) },
+ [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
+ [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
+ [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
+ [IMX7_RESET_PCIEPHY]= { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
+ [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
+ [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+ [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
+ [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
+};
+
+static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
+{
+ struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ const struct imx7_src_signal *sig = imx7_src_signals;
+ u32 val;
+
+ if (rst->id >= IMX7_RESET_NUM)
+ return -EINVAL;
+
+ if (rst->id == IMX7_RESET_PCIEPHY) {
+ /*
+* wait for more than 10us to release phy g_rst and
+* btnrst
+*/
+ udelay(10);
+ }
+
+ val = readl(priv->base + sig[rst->id].offset);
+
