[U-Boot] [PATCH 1/3 v4] ppc4xx: Add AMCC Arches board support (dual 460GT)
The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
FLASH, UART, EEPROM and temperature sensor, along with a shared debug
port. The two 460GT's will communicate with each other via shared
memory, Gigabit Ethernet and x1 PCI-Express.
Signed-off-by: Adam Graham [EMAIL PROTECTED]
Signed-off-by: Victor Gallardo [EMAIL PROTECTED]
---
v2:
- Added Arches (460GT) support to the existing Canyonlands (460) board
files since the Canyonlands board files support all current AMCC
PPC460EX/GT boards.
v3:
- Correct tab/spaces in canyonlands.h file.
v4:
- Fix commit text (line to long)
- remove unneed timeout for ETH_PLL lock
- remove CONFIG_EXTRA_ENV_SETTINGS from USB connectivity section
- seperated CONFIG_CMD_xxx on a per board bases
- Use ethprime to set Arches default ethernet port to 1
v5:
- No changes.
MAKEALL |1 +
Makefile |3 +-
board/amcc/canyonlands/canyonlands.c | 140 ++
board/amcc/canyonlands/init.S| 17 +++
include/configs/amcc-common.h| 17 +++-
include/configs/canyonlands.h| 219 +++---
include/ppc440.h |3 +
7 files changed, 383 insertions(+), 17 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 9ccb9ac..847c1fa 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -161,6 +161,7 @@ LIST_4xx= \
alpr\
AP1000 \
AR405 \
+ arches \
ASH405 \
bamboo \
bamboo_nand \
diff --git a/Makefile b/Makefile
index 7c13ce8..2af11c4 100644
--- a/Makefile
+++ b/Makefile
@@ -1206,7 +1206,8 @@ bubinga_config: unconfig
CANBT_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
-# Canyonlands Glacier use different U-Boot images
+# Arches, Canyonlands Glacier use different U-Boot images
+arches_config \
canyonlands_config \
glacier_config:unconfig
@mkdir -p $(obj)include
diff --git a/board/amcc/canyonlands/canyonlands.c
b/board/amcc/canyonlands/canyonlands.c
index e9eba49..b6ee2ab 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -38,11 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
#define BOARD_GLACIER 3
+#define BOARD_ARCHES 4
+
+#if defined(CONFIG_ARCHES)
+/*
+ * FPGA read/write helper macros
+ */
+static inline int board_fpga_read(int offset)
+{
+ int data;
+
+ data = in_8((void *)(CFG_FPGA_BASE + offset));
+
+ return data;
+}
+
+static inline void board_fpga_write(int offset, int data)
+{
+ out_8((void *)(CFG_FPGA_BASE + offset), data);
+}
+
+/*
+ * CPLD read/write helper macros
+ */
+static inline int board_cpld_read(int offset)
+{
+ int data;
+
+ out_8((void *)(CFG_CPLD_ADDR), offset);
+ data = in_8((void *)(CFG_CPLD_DATA));
+
+ return data;
+}
+
+static inline void board_cpld_write(int offset, int data)
+{
+ out_8((void *)(CFG_CPLD_ADDR), offset);
+ out_8((void *)(CFG_CPLD_DATA), data);
+}
+#endif /* defined(CONFIG_ARCHES) */
int board_early_init_f(void)
{
+#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
u32 pvr = get_pvr();
+#endif
/*
* Setup the interrupt controller polarities, triggers, etc.
@@ -79,6 +120,7 @@ int board_early_init_f(void)
mtdcr(uic3vr, 0x); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0x); /* clear all */
+#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */
mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL|
@@ -88,6 +130,7 @@ int board_early_init_f(void)
SDR0_CUST0_NDFC_BAC_ENCODE(3) |
(0x8000 (28 + CFG_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
+#endif
/*
* Configure PFC (Pin Function Control) registers
@@ -98,6 +141,7 @@ int board_early_init_f(void)
/* Enable PCI host functionality in SDR0_PCI0 */
mtsdr(SDR0_PCI0, 0xe000);
+#if !defined(CONFIG_ARCHES)
/* Enable ethernet and take out of reset */
out_8((void *)CFG_BCSR_BASE + 6, 0);
@@ -123,10 +167,12 @@ int board_early_init_f(void)
gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
}
+#endif
return 0;
}
+#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
u32 reg;
@@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type)
SDR_WRITE(SDR0_SRST1, 0x);
}
}
+#endif /* !defined(CONFIG_ARCHES) */
+
[U-Boot] [PATCH 1/3 v4] ppc4xx: Add AMCC Arches board support (dual 460GT)
The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
FLASH, UART, EEPROM and temperature sensor, along with a shared debug
port. The two 460GT's will communicate with each other via shared
memory, Gigabit Ethernet and x1 PCI-Express.
Signed-off-by: Adam Graham [EMAIL PROTECTED]
Signed-off-by: Victor Gallardo [EMAIL PROTECTED]
---
v2:
- Added Arches (460GT) support to the existing Canyonlands (460) board
files since the Canyonlands board files support all current AMCC
PPC460EX/GT boards.
v3:
- Correct tab/spaces in canyonlands.h file.
v4:
- Fix commit text (line to long)
- remove unneed timeout for ETH_PLL lock
- remove CONFIG_EXTRA_ENV_SETTINGS from USB connectivity section
- seperated CONFIG_CMD_xxx on a per board bases
- Use ethprime to set Arches default ethernet port to 1
MAKEALL |1 +
Makefile |3 +-
board/amcc/canyonlands/canyonlands.c | 140 ++
board/amcc/canyonlands/init.S| 17 +++
include/configs/amcc-common.h| 17 +++-
include/configs/canyonlands.h| 219 +++---
include/ppc440.h |3 +
7 files changed, 383 insertions(+), 17 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 9ccb9ac..847c1fa 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -161,6 +161,7 @@ LIST_4xx= \
alpr\
AP1000 \
AR405 \
+ arches \
ASH405 \
bamboo \
bamboo_nand \
diff --git a/Makefile b/Makefile
index 7c13ce8..2af11c4 100644
--- a/Makefile
+++ b/Makefile
@@ -1206,7 +1206,8 @@ bubinga_config: unconfig
CANBT_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
-# Canyonlands Glacier use different U-Boot images
+# Arches, Canyonlands Glacier use different U-Boot images
+arches_config \
canyonlands_config \
glacier_config:unconfig
@mkdir -p $(obj)include
diff --git a/board/amcc/canyonlands/canyonlands.c
b/board/amcc/canyonlands/canyonlands.c
index e9eba49..b6ee2ab 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -38,11 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
#define BOARD_GLACIER 3
+#define BOARD_ARCHES 4
+
+#if defined(CONFIG_ARCHES)
+/*
+ * FPGA read/write helper macros
+ */
+static inline int board_fpga_read(int offset)
+{
+ int data;
+
+ data = in_8((void *)(CFG_FPGA_BASE + offset));
+
+ return data;
+}
+
+static inline void board_fpga_write(int offset, int data)
+{
+ out_8((void *)(CFG_FPGA_BASE + offset), data);
+}
+
+/*
+ * CPLD read/write helper macros
+ */
+static inline int board_cpld_read(int offset)
+{
+ int data;
+
+ out_8((void *)(CFG_CPLD_ADDR), offset);
+ data = in_8((void *)(CFG_CPLD_DATA));
+
+ return data;
+}
+
+static inline void board_cpld_write(int offset, int data)
+{
+ out_8((void *)(CFG_CPLD_ADDR), offset);
+ out_8((void *)(CFG_CPLD_DATA), data);
+}
+#endif /* defined(CONFIG_ARCHES) */
int board_early_init_f(void)
{
+#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
u32 pvr = get_pvr();
+#endif
/*
* Setup the interrupt controller polarities, triggers, etc.
@@ -79,6 +120,7 @@ int board_early_init_f(void)
mtdcr(uic3vr, 0x); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0x); /* clear all */
+#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */
mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL|
@@ -88,6 +130,7 @@ int board_early_init_f(void)
SDR0_CUST0_NDFC_BAC_ENCODE(3) |
(0x8000 (28 + CFG_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
+#endif
/*
* Configure PFC (Pin Function Control) registers
@@ -98,6 +141,7 @@ int board_early_init_f(void)
/* Enable PCI host functionality in SDR0_PCI0 */
mtsdr(SDR0_PCI0, 0xe000);
+#if !defined(CONFIG_ARCHES)
/* Enable ethernet and take out of reset */
out_8((void *)CFG_BCSR_BASE + 6, 0);
@@ -123,10 +167,12 @@ int board_early_init_f(void)
gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
}
+#endif
return 0;
}
+#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
u32 reg;
@@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type)
SDR_WRITE(SDR0_SRST1, 0x);
}
}
+#endif /* !defined(CONFIG_ARCHES) */
+
+int get_cpu_num(void)
