Re: [U-Boot] [PATCH 1/4] Exynos: Add hardware accelerated SHA 256

2013-03-06 Thread Akshay Saraswat 
Hi Kim,

On Fri, 1 Mar 2013 16:11:36 +
Akshay Saraswat aksha...@samsung.com wrote:

 Samsung Enterprise Portal mySingle
 
  
 
 Hi Kim,
 
  
 
 On Thu, 28 Feb 2013 11:08:21 +
 
 Akshay Saraswat aksha...@samsung.com wrote:
 
As you can see, no.  It looks like you didn't change anything.  I
have to manually single-space things below.

  So, I have incremented this value
  to 500 which shall be good enough for the lowest of all frequencies. But 
  I guess what we
  need here is some formula, to calculate timeout on the basis of 
  frequency, which is nowhere
  defined.
 
 That's odd - I see a bunch of frequencies advertised in
 arch/arm/cpu/armv7/exynos/clock.c.
 Or how about using a cycle counter instead?
 btw, where can I find documentation for the ACE?
 
 I tried with different frequencies and data sizes and found that it takes 2 
 to 3 msecs in all the cases.
 Since, it is hardware accelerated encoding it is supposed to behave in this 
 same manner.
 But the current version of u-boot behaves mysteriously and slow downs when 
 pressed enter for long.
 In the above case mentioned I even saw time took to be more than 100 msecs 
 for all the cases.
 I think it would not be a better idea to timeout encoding acceleration.
 But still if it is needed, cycle counter suggestion would be a great 
 solution.

it depends on whether the h/w can fault during its operation.

 You can read Exynos5250 manual's Security subsystem section, which I 
 referred for this.

you mean this?:

http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_Dual_User_Manaul_Public_REV100-0.pdf

Yes, this is the manual. But this ine is just a part of it which has been made 
public by Samsung.
The one I have has 64 chapters in it and security subsystems is the 57th 
chapter.


There is no Security subsystem section.

Kim


Regards,
Akshay Saraswat
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Re: [U-Boot] [PATCH 1/4] Exynos: Add hardware accelerated SHA 256

2013-03-04 Thread Kim Phillips 
On Fri, 1 Mar 2013 16:11:36 +
Akshay Saraswat aksha...@samsung.com wrote:

 Samsung Enterprise Portal mySingle
 
  
 
 Hi Kim,
 
  
 
 On Thu, 28 Feb 2013 11:08:21 +
 
 Akshay Saraswat aksha...@samsung.com wrote:
 
 
 
  On Wed, 27 Feb 2013 10:24:39 -0500
 
 
 
  Akshay Saraswat aksha...@samsung.com wrote:
 
 
 
 can you fix your mailer to not double space lines?
 
  
 
 Sorry for the disarranged text. I hope this time it is good.
 
  

As you can see, no.  It looks like you didn't change anything.  I
have to manually single-space things below.

  So, I have incremented this value
  to 500 which shall be good enough for the lowest of all frequencies. But I 
  guess what we
  need here is some formula, to calculate timeout on the basis of frequency, 
  which is nowhere
  defined.
 
 That's odd - I see a bunch of frequencies advertised in
 arch/arm/cpu/armv7/exynos/clock.c.
 Or how about using a cycle counter instead?
 btw, where can I find documentation for the ACE?
 
 I tried with different frequencies and data sizes and found that it takes 2 
 to 3 msecs in all the cases.
 Since, it is hardware accelerated encoding it is supposed to behave in this 
 same manner.
 But the current version of u-boot behaves mysteriously and slow downs when 
 pressed enter for long.
 In the above case mentioned I even saw time took to be more than 100 msecs 
 for all the cases.
 I think it would not be a better idea to timeout encoding acceleration.
 But still if it is needed, cycle counter suggestion would be a great solution.

it depends on whether the h/w can fault during its operation.

 You can read Exynos5250 manual's Security subsystem section, which I 
 referred for this.

you mean this?:

http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_Dual_User_Manaul_Public_REV100-0.pdf

There is no Security subsystem section.

Kim

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Re: [U-Boot] [PATCH 1/4] Exynos: Add hardware accelerated SHA 256

2013-02-28 Thread Kim Phillips 
On Thu, 28 Feb 2013 11:08:21 +
Akshay Saraswat aksha...@samsung.com wrote:

 On Wed, 27 Feb 2013 10:24:39 -0500
 
 Akshay Saraswat aksha...@samsung.com wrote:

can you fix your mailer to not double space lines?

  +/* Maximum input data size is 8 MB. Timeout observed for data size above 
  8MB */
  +#define TIMEOUT_MS  100
 
 So if there's a drop in processor frequency, the driver times out
 too early?  Not good.
 
 Right now we dont have any way to calculate the timeout.

not even empirically?

 So, I have incremented this value
 to 500 which shall be good enough for the lowest of all frequencies. But I 
 guess what we
 need here is some formula, to calculate timeout on the basis of frequency, 
 which is nowhere
 defined.

That's odd - I see a bunch of frequencies advertised in
arch/arm/cpu/armv7/exynos/clock.c.

Or how about using a cycle counter instead?

btw, where can I find documentation for the ACE?

Kim

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[U-Boot] [PATCH 1/4] Exynos: Add hardware accelerated SHA 256

2013-02-27 Thread Akshay Saraswat 
SHA-256 and SHA-1 accelerated using ACE hardware.

TEST=sha256 0x40008000 0x2B 0x40009000
Used mm and md to write a standard string to memory location
0x40008000 and ran the above command to verify the output.

Signed-off-by: ARUN MANKUZHI aru...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
 arch/arm/cpu/armv7/exynos/Makefile |   4 +
 arch/arm/cpu/armv7/exynos/ace_sha.c| 118 +++
 arch/arm/include/asm/arch-exynos/ace_sfr.h | 310 +
 arch/arm/include/asm/arch-exynos/ace_sha.h |  41 
 arch/arm/include/asm/arch-exynos/cpu.h |   4 +
 5 files changed, 477 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/exynos/ace_sha.c
 create mode 100644 arch/arm/include/asm/arch-exynos/ace_sfr.h
 create mode 100644 arch/arm/include/asm/arch-exynos/ace_sha.h

diff --git a/arch/arm/cpu/armv7/exynos/Makefile 
b/arch/arm/cpu/armv7/exynos/Makefile
index 9119961..0a93a52 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -24,6 +24,10 @@ LIB  = $(obj)lib$(SOC).o
 
 COBJS  += clock.o power.o soc.o system.o pinmux.o
 
+ifdef CONFIG_EXYNOS_ACE_SHA
+COBJS += ace_sha.o
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
 
diff --git a/arch/arm/cpu/armv7/exynos/ace_sha.c 
b/arch/arm/cpu/armv7/exynos/ace_sha.c
new file mode 100644
index 000..2715a03
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/ace_sha.c
@@ -0,0 +1,118 @@
+/*
+ * Advanced Crypto Engine - SHA Firmware
+ *
+ * Copyright (c) 2012  Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include common.h
+#include asm/arch/ace_sha.h
+#include asm/arch/ace_sfr.h
+
+/* Maximum input data size is 8 MB. Timeout observed for data size above 8MB */
+#define TIMEOUT_MS 100
+
+#define SHA1_DIGEST_LEN20
+#define SHA256_DIGEST_LEN  32
+
+/* SHA1 value for the message of zero length */
+static const unsigned char sha1_digest_emptymsg[SHA1_DIGEST_LEN] = {
+   0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
+   0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
+   0xAF, 0xD8, 0x07, 0x09};
+
+/* SHA256 value for the message of zero length */
+static const unsigned char sha256_digest_emptymsg[SHA256_DIGEST_LEN] = {
+   0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
+   0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
+   0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
+   0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
+
+int ace_sha_hash_digest(
+   unsigned char *pout, unsigned char *pbuf,
+   unsigned int buf_len, unsigned int hash_type)
+{
+   unsigned int i, reg, len;
+   unsigned int *pdigest;
+   ulong start;
+   struct exynos_ace_sfr *ace_sha_reg =
+   (struct exynos_ace_sfr *) samsung_get_base_ace_sfr();
+
+   if (buf_len == 0) {
+   /* ACE H/W cannot compute hash value for empty string */
+   if (hash_type == ACE_SHA_TYPE_SHA1)
+   memcpy(pout, sha1_digest_emptymsg, SHA1_DIGEST_LEN);
+   else
+   memcpy(pout, sha256_digest_emptymsg, SHA256_DIGEST_LEN);
+   return 0;
+   }
+
+   /* Flush HRDMA */
+   writel(ACE_FC_HRDMACFLUSH_ON, ace_sha_reg-fc_hrdmac);
+   writel(ACE_FC_HRDMACFLUSH_OFF, ace_sha_reg-fc_hrdmac);
+
+   /* Set byte swap of data in */
+   writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
+   ace_sha_reg-hash_byteswap);
+
+   /* Select Hash input mux as external source */
+   reg = readl(ace_sha_reg-fc_fifoctrl);
+   reg = (reg  ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
+   writel(reg, ace_sha_reg-fc_fifoctrl);
+
+   /* Set Hash as SHA1 or SHA256 and start Hash engine */
+   reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
+   ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
+   reg |= ACE_HASH_STARTBIT_ON;
+   writel(reg, ace_sha_reg-hash_control);
+
+   /* Enable FIFO mode */
+   writel(ACE_HASH_FIFO_ON, ace_sha_reg-hash_fifo_mode);
+
+   /* Set message length */
+   writel(buf_len, ace_sha_reg-hash_msgsize_low);
+   writel(0, ace_sha_reg-hash_msgsize_high);
+
+   /* Set HRDMA */
+

Re: [U-Boot] [PATCH 1/4] Exynos: Add hardware accelerated SHA 256

2013-02-27 Thread Kim Phillips 
On Wed, 27 Feb 2013 10:24:39 -0500
Akshay Saraswat aksha...@samsung.com wrote:

 SHA-256 and SHA-1 accelerated using ACE hardware.
 
 TEST=sha256 0x40008000 0x2B 0x40009000
 Used mm and md to write a standard string to memory location
 0x40008000 and ran the above command to verify the output.

can we get rid of this TEST= infrastructure format?  It's not used
on upstream u-boot.

 Signed-off-by: ARUN MANKUZHI aru...@samsung.com
 Signed-off-by: Akshay Saraswat aksha...@samsung.com
 ---
  arch/arm/cpu/armv7/exynos/Makefile |   4 +
  arch/arm/cpu/armv7/exynos/ace_sha.c| 118 +++
  arch/arm/include/asm/arch-exynos/ace_sfr.h | 310 
 +
  arch/arm/include/asm/arch-exynos/ace_sha.h |  41 
  arch/arm/include/asm/arch-exynos/cpu.h |   4 +
  5 files changed, 477 insertions(+)
  create mode 100644 arch/arm/cpu/armv7/exynos/ace_sha.c
  create mode 100644 arch/arm/include/asm/arch-exynos/ace_sfr.h
  create mode 100644 arch/arm/include/asm/arch-exynos/ace_sha.h

I doubt there's anything binding this to arch-exynos, and I bet the
h/w is going to be available - if not already - on some other parts,
so it probably belongs in a new drivers/crypto directory.

 +/* Maximum input data size is 8 MB. Timeout observed for data size above 8MB 
 */
 +#define TIMEOUT_MS   100

So if there's a drop in processor frequency, the driver times out
too early?  Not good.

 +#define SHA1_DIGEST_LEN  20
 +#define SHA256_DIGEST_LEN32

don't duplicate definitions that already exist in include/sha*.h.

 + if (buf_len == 0) {
 + /* ACE H/W cannot compute hash value for empty string */
 + if (hash_type == ACE_SHA_TYPE_SHA1)
 + memcpy(pout, sha1_digest_emptymsg, SHA1_DIGEST_LEN);
 + else
 + memcpy(pout, sha256_digest_emptymsg, SHA256_DIGEST_LEN);
 + return 0;
 + }

there's no protection from buf_len going over the h/w 8MB limit
mentioned above - why not fall back to the s/w implementation in
both those cases?  Or, if the h/w can be programmed to perform
multiple hash updates in 8MB data chunks, add support to do that.

 + /* Read hash result */
 + pdigest = (unsigned int *)pout;
 + len = (hash_type == ACE_SHA_TYPE_SHA1) ? 5 : 8;

magic numbers - use SHAx_SUM_LEN / 4.

Kim

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