[U-Boot] [PATCH 1/4 v6] Exynos: Add hardware accelerated SHA256 and SHA1
SHA-256 and SHA-1 accelerated using ACE hardware.
Signed-off-by: ARUN MANKUZHI aru...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- Moved code to drivers/crypto.
- Fixed few other nits.
Changes since v2:
- Added falling back to software sha256 in case length exceeds buffer
limit.
- Reduced one tab at lines 533, 559 and 571 in this patch.
- Removed space after a cast at line 506 in this patch.
- Removed blank line at line 561 in this patch.
- Removed space before semicolon at line 576 in this patch.
Changes since v3:
- Removed buffer limit since there are 2 regs for address
hash_msg_size_high and low.
That means buffer length could go upto 2^64 bits which is practically
- Removed falling back to software sha256 because there is no buffer
limit.
- Removed / 4 to sha1 and sha256 lengths and added increment to 4 in
for
loop at line 573.
- Timed out still kept to be 100 ms since this is enough for hardware
to switch
status to idle from busy.
In case it couldn't that means h/w is faulty.
Changes since v4:
- Added include for clk.h.
- Added define for MAX_FREQ.
- Added timeout calculation as per frequency.
- Changed i+=4 to i++ and len to len/4 in for loop at line 591
in this patch.
- Added two new functions ace_sha256 and ace_sha1.
Changes since v5:
- Removed ace_sha.h.
- Renamed ace_sfr.h as ace_sha.h.
- Removed timeout and checking for PRNG_ERROR bit in HASH_STATUS
register.
PRNG_ERROR bit high means setup was not done properly. Since there is
no
way to detect faulty h/w, we consider the possible fact that h/w
should
not be able to setup feed properly if it's faulty.
- Renamed function name ace_sha256 to hw_sha256 and ace_sha1 to hw_sha1.
Makefile | 1 +
arch/arm/include/asm/arch-exynos/ace_sha.h | 327 +
arch/arm/include/asm/arch-exynos/cpu.h | 4 +
drivers/crypto/Makefile| 47 +
drivers/crypto/ace_sha.c | 129
5 files changed, 508 insertions(+)
create mode 100644 arch/arm/include/asm/arch-exynos/ace_sha.h
create mode 100644 drivers/crypto/Makefile
create mode 100644 drivers/crypto/ace_sha.c
diff --git a/Makefile b/Makefile
index fc18dd4..4c41130 100644
--- a/Makefile
+++ b/Makefile
@@ -272,6 +272,7 @@ LIBS-y += disk/libdisk.o
LIBS-y += drivers/bios_emulator/libatibiosemu.o
LIBS-y += drivers/block/libblock.o
LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
+LIBS-y += drivers/crypto/libcrypto.o
LIBS-y += drivers/dma/libdma.o
LIBS-y += drivers/fpga/libfpga.o
LIBS-y += drivers/gpio/libgpio.o
diff --git a/arch/arm/include/asm/arch-exynos/ace_sha.h
b/arch/arm/include/asm/arch-exynos/ace_sha.h
new file mode 100644
index 000..259f3d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/ace_sha.h
@@ -0,0 +1,327 @@
+/*
+ * Header file for Advanced Crypto Engine - SFR definitions
+ *
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ACE_SHA_H
+#define __ACE_SHA_H
+
+struct exynos_ace_sfr {
+ unsigned intfc_intstat; /* base + 0 */
+ unsigned intfc_intenset;
+ unsigned intfc_intenclr;
+ unsigned intfc_intpend;
+ unsigned intfc_fifostat;
+ unsigned intfc_fifoctrl;
+ unsigned intfc_global;
+ unsigned intres1;
+ unsigned intfc_brdmas;
+ unsigned intfc_brdmal;
+ unsigned intfc_brdmac;
+ unsigned intres2;
+ unsigned intfc_btdmas;
+ unsigned intfc_btdmal;
+ unsigned intfc_btdmac;
+ unsigned intres3;
+ unsigned intfc_hrdmas;
+ unsigned intfc_hrdmal;
+ unsigned intfc_hrdmac;
+ unsigned intres4;
+ unsigned intfc_pkdmas;
+ unsigned intfc_pkdmal;
+ unsigned intfc_pkdmac;
+ unsigned intfc_pkdmao;
+ unsigned char res5[0x1a0];
+
+ unsigned intaes_control;/* base + 0x200 */
+ unsigned int
Re: [U-Boot] [PATCH 1/4 v6] Exynos: Add hardware accelerated SHA256 and SHA1
Hi Akshay,
On Fri, Mar 15, 2013 at 1:52 AM, Akshay Saraswat aksha...@samsung.com wrote:
SHA-256 and SHA-1 accelerated using ACE hardware.
Signed-off-by: ARUN MANKUZHI aru...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
One nit below, but otherwise:
Acked-by: Simon Glass s...@chromium.org
[...]
Changes since v5:
- Removed ace_sha.h.
- Renamed ace_sfr.h as ace_sha.h.
- Removed timeout and checking for PRNG_ERROR bit in HASH_STATUS
register.
PRNG_ERROR bit high means setup was not done properly. Since there
is no
way to detect faulty h/w, we consider the possible fact that h/w
should
not be able to setup feed properly if it's faulty.
- Renamed function name ace_sha256 to hw_sha256 and ace_sha1 to
hw_sha1.
Makefile | 1 +
arch/arm/include/asm/arch-exynos/ace_sha.h | 327
+
arch/arm/include/asm/arch-exynos/cpu.h | 4 +
drivers/crypto/Makefile| 47 +
drivers/crypto/ace_sha.c | 129
5 files changed, 508 insertions(+)
create mode 100644 arch/arm/include/asm/arch-exynos/ace_sha.h
create mode 100644 drivers/crypto/Makefile
create mode 100644 drivers/crypto/ace_sha.c
[...]
diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c
new file mode 100644
index 000..e8d9b2d
--- /dev/null
+++ b/drivers/crypto/ace_sha.c
@@ -0,0 +1,129 @@
+/*
+ * Advanced Crypto Engine - SHA Firmware
+ * Copyright (c) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include common.h
+#include sha256.h
+#include sha1.h
+#include asm/errno.h
+#include asm/arch/clk.h
+#include asm/arch/ace_sha.h
+
+/* Maximum frequency supported by the SoC*/
+#define MAX_FREQ (1.7 * 1000 * 1000 * 1000)
+
+/* SHA1 value for the message of zero length */
+static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
+ 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
+ 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
+ 0xAF, 0xD8, 0x07, 0x09};
+
+/* SHA256 value for the message of zero length */
+static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
+ 0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
+ 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
+ 0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
+ 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
+
+int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
+ unsigned char *pout, unsigned int hash_type)
Since you don't check the return value and it only ever return 0, you
may as well make this void.
+{
+ unsigned int i, reg, len;
+ unsigned int *pdigest;
+ struct exynos_ace_sfr *ace_sha_reg =
+ (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
+
+ if (buf_len == 0) {
+ /* ACE H/W cannot compute hash value for empty string */
+ if (hash_type == ACE_SHA_TYPE_SHA1)
+ memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
+ else
+ memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
+ return 0;
+ }
+
+ /* Flush HRDMA */
+ writel(ACE_FC_HRDMACFLUSH_ON, ace_sha_reg-fc_hrdmac);
+ writel(ACE_FC_HRDMACFLUSH_OFF, ace_sha_reg-fc_hrdmac);
+
+ /* Set byte swap of data in */
+ writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
+ ace_sha_reg-hash_byteswap);
+
+ /* Select Hash input mux as external source */
+ reg = readl(ace_sha_reg-fc_fifoctrl);
+ reg = (reg ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
+ writel(reg, ace_sha_reg-fc_fifoctrl);
+
+ /* Set Hash as SHA1 or SHA256 and start Hash engine */
+ reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
+ ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
+ reg |= ACE_HASH_STARTBIT_ON;
+ writel(reg, ace_sha_reg-hash_control);
+
+ /* Enable FIFO mode */
+ writel(ACE_HASH_FIFO_ON, ace_sha_reg-hash_fifo_mode);
+
+ /* Set message length */
+
