Re: [U-Boot] [PATCH 11/22] imx8m: add pin header for i.MX8MM

2019-08-13 Thread Peng Fan 
Hi Lukasz,

> -Original Message-
> From: Lukasz Majewski 
> Sent: 2019年8月12日 5:56
> To: Peng Fan 
> Cc: sba...@denx.de; feste...@gmail.com; dl-uboot-imx
> ; u-boot@lists.denx.de; frieder.schre...@kontron.de
> Subject: Re: [PATCH 11/22] imx8m: add pin header for i.MX8MM
> 
> Hi Peng,
> 
> > Add pin header file for i.MX8MM
> >
> 
> What is the origin (e.g. SHA1, branch) of this file?

This file is dedicated for U-Boot, not imported.

Regards,
Peng.

> 
> > To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION
> needs to be
> > selected.
> >
> > Signed-off-by: Peng Fan 
> > ---
> >  arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691
> > ++ 1 file changed, 691 insertions(+)
> >  create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> >
> > diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> > b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h new file mode
> 100644
> > index 00..210e96e1db
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> > @@ -0,0 +1,691 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2018-2019 NXP
> > + */
> > +
> > +#ifndef __ASM_ARCH_IMX8MM_PINS_H__
> > +#define __ASM_ARCH_IMX8MM_PINS_H__
> > +
> > +#include 
> > +
> > +enum {
> > +   IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0
> >  =  IOMUX_PAD(0x0290, 0x0028, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT
> >  =  IOMUX_PAD(0x0290, 0x0028, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K
> >  =  IOMUX_PAD(0x0290, 0x0028, 5, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1
> >  =  IOMUX_PAD(0x0290, 0x0028, 6, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1
> >  =  IOMUX_PAD(0x0294, 0x002C, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO01_PWM1_OUT
> >  =  IOMUX_PAD(0x0294, 0x002C, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M
> >  =  IOMUX_PAD(0x0294, 0x002C, 5, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2
> >  =  IOMUX_PAD(0x0294, 0x002C, 6, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2
> >  =  IOMUX_PAD(0x0298, 0x0030, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B
> >  =  IOMUX_PAD(0x0298, 0x0030, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY
> >  =  IOMUX_PAD(0x0298, 0x0030, 5, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3
> >  =  IOMUX_PAD(0x029C, 0x0034, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT
> >  =  IOMUX_PAD(0x029C, 0x0034, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0
> >  =  IOMUX_PAD(0x029C, 0x0034, 5, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4
> >  =  IOMUX_PAD(0x02A0, 0x0038, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT
> >  =  IOMUX_PAD(0x02A0, 0x0038, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1
> >  =  IOMUX_PAD(0x02A0, 0x0038, 5, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5
> >  =  IOMUX_PAD(0x02A4, 0x003C, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI
> >  =  IOMUX_PAD(0x02A4, 0x003C, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY
> >  =  IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT
> >  =  IOMUX_PAD(0x02A4, 0x003C, 6, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6
> >  =  IOMUX_PAD(0x02A8, 0x0040, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO06_ENET1_MDC
> >  =  IOMUX_PAD(0x02A8, 0x0040, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B
> >  =  IOMUX_PAD(0x02A8, 0x0040, 5, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3
> >  =  IOMUX_PAD(0x02A8, 0x0040, 6, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7
> >  =  IOMUX_PAD(0x02AC, 0x0044, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO
> >  =  IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO07_USDHC1_WP
> >  =  IOMUX_PAD(0x02AC, 0x0044, 5, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4
> >  =  IOMUX_PAD(0x02AC, 0x0044, 6, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8
> >  =  IOMUX_PAD(0x02B0, 0x0048, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN
> >  =  IOMUX_PAD(0x02B0, 0x0048, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B
> >  =  IOMUX_PAD(0x02B0, 0x0048, 5, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO08_CCM_WAIT
> >  =  IOMUX_PAD(0x02B0, 0x0048, 6, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9
> >  =  IOMUX_PAD(0x02B4, 0x004C, 0, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT
> >  =  IOMUX_PAD(0x02B4, 0x004C, 1, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B
> >  =  IOMUX_PAD(0x02B4, 0x004C, 4, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0
> >  =  IOMUX_PAD(0x02B4, 0x004C, 5, 0x, 0, 0),
> > +   IMX8MM_PAD_GPIO1_IO09_CCM_STOP
> >  =  IOMUX_PAD(0x02B4, 0x004C, 6, 0x, 0, 0), +
> > +   IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10
> >  =  IOMUX_PAD(0x02B8,

Re: [U-Boot] [PATCH 11/22] imx8m: add pin header for i.MX8MM

2019-08-11 Thread Lukasz Majewski 
Hi Peng,

> Add pin header file for i.MX8MM
> 

What is the origin (e.g. SHA1, branch) of this file?

> To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
> selected.
> 
> Signed-off-by: Peng Fan 
> ---
>  arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691
> ++ 1 file changed, 691 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> 
> diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h new file mode 100644
> index 00..210e96e1db
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> @@ -0,0 +1,691 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018-2019 NXP
> + */
> +
> +#ifndef __ASM_ARCH_IMX8MM_PINS_H__
> +#define __ASM_ARCH_IMX8MM_PINS_H__
> +
> +#include 
> +
> +enum {
> + IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0
>  =  IOMUX_PAD(0x0290, 0x0028, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT
>  =  IOMUX_PAD(0x0290, 0x0028, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K
>  =  IOMUX_PAD(0x0290, 0x0028, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1
>  =  IOMUX_PAD(0x0290, 0x0028, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1
>  =  IOMUX_PAD(0x0294, 0x002C, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO01_PWM1_OUT
>  =  IOMUX_PAD(0x0294, 0x002C, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M
>  =  IOMUX_PAD(0x0294, 0x002C, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2
>  =  IOMUX_PAD(0x0294, 0x002C, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2
>  =  IOMUX_PAD(0x0298, 0x0030, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B
>  =  IOMUX_PAD(0x0298, 0x0030, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY
>  =  IOMUX_PAD(0x0298, 0x0030, 5, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3
>  =  IOMUX_PAD(0x029C, 0x0034, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT
>  =  IOMUX_PAD(0x029C, 0x0034, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0
>  =  IOMUX_PAD(0x029C, 0x0034, 5, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4
>  =  IOMUX_PAD(0x02A0, 0x0038, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT
>  =  IOMUX_PAD(0x02A0, 0x0038, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1
>  =  IOMUX_PAD(0x02A0, 0x0038, 5, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5
>  =  IOMUX_PAD(0x02A4, 0x003C, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI
>  =  IOMUX_PAD(0x02A4, 0x003C, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY
>  =  IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
> + IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT
>  =  IOMUX_PAD(0x02A4, 0x003C, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6
>  =  IOMUX_PAD(0x02A8, 0x0040, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO06_ENET1_MDC
>  =  IOMUX_PAD(0x02A8, 0x0040, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B
>  =  IOMUX_PAD(0x02A8, 0x0040, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3
>  =  IOMUX_PAD(0x02A8, 0x0040, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7
>  =  IOMUX_PAD(0x02AC, 0x0044, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO
>  =  IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
> + IMX8MM_PAD_GPIO1_IO07_USDHC1_WP
>  =  IOMUX_PAD(0x02AC, 0x0044, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4
>  =  IOMUX_PAD(0x02AC, 0x0044, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8
>  =  IOMUX_PAD(0x02B0, 0x0048, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN
>  =  IOMUX_PAD(0x02B0, 0x0048, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B
>  =  IOMUX_PAD(0x02B0, 0x0048, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO08_CCM_WAIT
>  =  IOMUX_PAD(0x02B0, 0x0048, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9
>  =  IOMUX_PAD(0x02B4, 0x004C, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT
>  =  IOMUX_PAD(0x02B4, 0x004C, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B
>  =  IOMUX_PAD(0x02B4, 0x004C, 4, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0
>  =  IOMUX_PAD(0x02B4, 0x004C, 5, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO09_CCM_STOP
>  =  IOMUX_PAD(0x02B4, 0x004C, 6, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10
>  =  IOMUX_PAD(0x02B8, 0x0050, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID
>  =  IOMUX_PAD(0x02B8, 0x0050, 1, 0x, 0, 0), +
> + IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11
>  =  IOMUX_PAD(0x02BC, 0x0054, 0, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID
>  =  IOMUX_PAD(0x02BC, 0x0054, 1, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT
>  =  IOMUX_PAD(0x02BC, 0x0054, 4, 0x, 0, 0),
> + IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY
>  =  IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
> +

[U-Boot] [PATCH 11/22] imx8m: add pin header for i.MX8MM

2019-08-08 Thread Peng Fan 
Add pin header file for i.MX8MM

To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.

Signed-off-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 ++
 1 file changed, 691 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h

diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h 
b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
new file mode 100644
index 00..210e96e1db
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
@@ -0,0 +1,691 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MM_PINS_H__
+#define __ASM_ARCH_IMX8MM_PINS_H__
+
+#include 
+
+enum {
+   IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0   =  
IOMUX_PAD(0x0290, 0x0028, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT   =  
IOMUX_PAD(0x0290, 0x0028, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K =  
IOMUX_PAD(0x0290, 0x0028, 5, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1=  
IOMUX_PAD(0x0290, 0x0028, 6, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1   =  
IOMUX_PAD(0x0294, 0x002C, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO01_PWM1_OUT=  
IOMUX_PAD(0x0294, 0x002C, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M =  
IOMUX_PAD(0x0294, 0x002C, 5, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2=  
IOMUX_PAD(0x0294, 0x002C, 6, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2   =  
IOMUX_PAD(0x0298, 0x0030, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B=  
IOMUX_PAD(0x0298, 0x0030, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY  =  
IOMUX_PAD(0x0298, 0x0030, 5, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3   =  
IOMUX_PAD(0x029C, 0x0034, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT  =  
IOMUX_PAD(0x029C, 0x0034, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0=  
IOMUX_PAD(0x029C, 0x0034, 5, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4   =  
IOMUX_PAD(0x02A0, 0x0038, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT  =  
IOMUX_PAD(0x02A0, 0x0038, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1=  
IOMUX_PAD(0x02A0, 0x0038, 5, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5   =  
IOMUX_PAD(0x02A4, 0x003C, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI =  
IOMUX_PAD(0x02A4, 0x003C, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY  =  
IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+   IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT=  
IOMUX_PAD(0x02A4, 0x003C, 6, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6   =  
IOMUX_PAD(0x02A8, 0x0040, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO06_ENET1_MDC   =  
IOMUX_PAD(0x02A8, 0x0040, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B =  
IOMUX_PAD(0x02A8, 0x0040, 5, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3=  
IOMUX_PAD(0x02A8, 0x0040, 6, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7   =  
IOMUX_PAD(0x02AC, 0x0044, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO  =  
IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+   IMX8MM_PAD_GPIO1_IO07_USDHC1_WP   =  
IOMUX_PAD(0x02AC, 0x0044, 5, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4=  
IOMUX_PAD(0x02AC, 0x0044, 6, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8   =  
IOMUX_PAD(0x02B0, 0x0048, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN=  
IOMUX_PAD(0x02B0, 0x0048, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B  =  
IOMUX_PAD(0x02B0, 0x0048, 5, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO08_CCM_WAIT=  
IOMUX_PAD(0x02B0, 0x0048, 6, 0x, 0, 0),
+
+   IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9   =  
IOMUX_PAD(0x02B4, 0x004C, 0, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT   =  
IOMUX_PAD(0x02B4, 0x004C, 1, 0x, 0, 0),
+   IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B  =  
IOMUX_PAD(0x02B4, 0x004C, 4, 0x,