Re: [U-Boot] [PATCH 18/22] imx8m: restructure clock.h
> Subject: Re: [PATCH 18/22] imx8m: restructure clock.h
>
> On Fri, 9 Aug 2019 04:15:37 +
> Peng Fan wrote:
>
> > i.MX8MQ and i.MX8MM use different analog pll design, but they share
> > same ccm design.
> > Add clock_imx8mq.h for i.MX8MQ
> > keep common part in clock.h
> >
> > Signed-off-by: Peng Fan
> > ---
> > arch/arm/include/asm/arch-imx8m/clock.h| 491
> > +++--
> > arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424
> > + arch/arm/mach-imx/imx8m/clock_imx8mq.c
> > | 5 +- 3 files changed, 467 insertions(+), 453 deletions(-) create
> > mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
> >
> > diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> > b/arch/arm/include/asm/arch-imx8m/clock.h index
> e7c1670f6b..7225c760fe
> > 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++
> > b/arch/arm/include/asm/arch-imx8m/clock.h @@ -1,28 +1,29 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> > - * Copyright 2017 NXP
> > - *
> > - * Peng Fan
> > + * Copyright 2017-2019 NXP
> > */
>
> Is there any problem to not add your name and Copyright?
Will fix.
Thanks,
Peng.
>
> >
> > -#ifndef _ASM_ARCH_IMX8M_CLOCK_H
> > -#define _ASM_ARCH_IMX8M_CLOCK_H
> > -
> > #include
> >
> > +#ifdef CONFIG_IMX8MQ
> > +#include
> > +#else
> > +#error "Error no clock.h"
> > +#endif
> > +
> > #define MHZ(X) ((X) * 100UL)
> >
> > -enum pll_clocks {
> > - ANATOP_ARM_PLL,
> > - ANATOP_GPU_PLL,
> > - ANATOP_SYSTEM_PLL1,
> > - ANATOP_SYSTEM_PLL2,
> > - ANATOP_SYSTEM_PLL3,
> > - ANATOP_AUDIO_PLL1,
> > - ANATOP_AUDIO_PLL2,
> > - ANATOP_VIDEO_PLL1,
> > - ANATOP_VIDEO_PLL2,
> > - ANATOP_DRAM_PLL,
> > +/* Mainly for compatible to imx common code. */ enum mxc_clock {
> > + MXC_ARM_CLK = 0,
> > + MXC_IPG_CLK,
> > + MXC_CSPI_CLK,
> > + MXC_ESDHC_CLK,
> > + MXC_ESDHC2_CLK,
> > + MXC_ESDHC3_CLK,
> > + MXC_I2C_CLK,
> > + MXC_UART_CLK,
> > + MXC_QSPI_CLK,
> > };
> >
> > enum clk_slice_type {
> > @@ -35,297 +36,6 @@ enum clk_slice_type {
> > DRAM_SEL_CLOCK_SLICE,
> > };
> >
> > -enum clk_root_index {
> > - MXC_ARM_CLK = 0,
> > - ARM_A53_CLK_ROOT= 0,
> > - ARM_M4_CLK_ROOT = 1,
> > - VPU_A53_CLK_ROOT= 2,
> > - GPU_CORE_CLK_ROOT = 3,
> > - GPU_SHADER_CLK_ROOT = 4,
> > - MAIN_AXI_CLK_ROOT = 16,
> > - ENET_AXI_CLK_ROOT = 17,
> > - NAND_USDHC_BUS_CLK_ROOT = 18,
> > - VPU_BUS_CLK_ROOT= 19,
> > - DISPLAY_AXI_CLK_ROOT= 20,
> > - DISPLAY_APB_CLK_ROOT= 21,
> > - DISPLAY_RTRM_CLK_ROOT = 22,
> > - USB_BUS_CLK_ROOT= 23,
> > - GPU_AXI_CLK_ROOT= 24,
> > - GPU_AHB_CLK_ROOT= 25,
> > - NOC_CLK_ROOT= 26,
> > - NOC_APB_CLK_ROOT= 27,
> > - AHB_CLK_ROOT= 32,
> > - IPG_CLK_ROOT= 33,
> > - MXC_IPG_CLK = 33,
> > - AUDIO_AHB_CLK_ROOT = 34,
> > - MIPI_DSI_ESC_RX_CLK_ROOT= 36,
> > - DRAM_SEL_CFG= 48,
> > - CORE_SEL_CFG= 49,
> > - DRAM_ALT_CLK_ROOT = 64,
> > - DRAM_APB_CLK_ROOT = 65,
> > - VPU_G1_CLK_ROOT = 66,
> > - VPU_G2_CLK_ROOT = 67,
> > - DISPLAY_DTRC_CLK_ROOT = 68,
> > - DISPLAY_DC8000_CLK_ROOT = 69,
> > - PCIE1_CTRL_CLK_ROOT = 70,
> > - PCIE1_PHY_CLK_ROOT = 71,
> > - PCIE1_AUX_CLK_ROOT = 72,
> > - DC_PIXEL_CLK_ROOT = 73,
> > - LCDIF_PIXEL_CLK_ROOT= 74,
> > - SAI1_CLK_ROOT = 75,
> > - SAI2_CLK_ROOT = 76,
> > - SAI3_CLK_ROOT = 77,
> > - SAI4_CLK_ROOT = 78,
> > - SAI5_CLK_ROOT = 79,
> > - SAI6_CLK_ROOT = 80,
> > - SPDIF1_CLK_ROOT = 81,
> > - SPDIF2_CLK_ROOT = 82,
> > - ENET_REF_CLK_ROOT = 83,
> > - ENET_TIMER_CLK_ROOT = 84,
> > - ENET_PHY_REF_CLK_ROOT = 85,
> > - NAND_CLK_ROOT = 86,
> > - QSPI_CLK_ROOT = 87,
> > - MXC_ESDHC_CLK = 88,
> > - USDHC1_CLK_ROOT = 88,
> > - MXC_ESDHC2_CLK = 89,
> > - USDHC2_CLK_ROOT = 89,
> > - I2C1_CLK_ROOT = 90,
> > - MXC_I2C_CLK = 90,
> > - I2C2_CLK_ROOT = 91,
> > - I2C3_CLK_ROOT = 92,
> > - I2C4_CLK_ROOT = 93,
> > - UART1_CLK_ROOT = 94,
> > - UART2_CLK_ROOT = 95,
> > - UART3_CLK_ROOT = 96,
> > - UART4_CLK_ROOT = 97,
> > -
Re: [U-Boot] [PATCH 18/22] imx8m: restructure clock.h
On Fri, 9 Aug 2019 04:15:37 +
Peng Fan wrote:
> i.MX8MQ and i.MX8MM use different analog pll design, but they
> share same ccm design.
> Add clock_imx8mq.h for i.MX8MQ
> keep common part in clock.h
>
> Signed-off-by: Peng Fan
> ---
> arch/arm/include/asm/arch-imx8m/clock.h| 491
> +++--
> arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424
> + arch/arm/mach-imx/imx8m/clock_imx8mq.c
> | 5 +- 3 files changed, 467 insertions(+), 453 deletions(-) create
> mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
>
> diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
> b/arch/arm/include/asm/arch-imx8m/clock.h index
> e7c1670f6b..7225c760fe 100644 ---
> a/arch/arm/include/asm/arch-imx8m/clock.h +++
> b/arch/arm/include/asm/arch-imx8m/clock.h @@ -1,28 +1,29 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> - * Copyright 2017 NXP
> - *
> - * Peng Fan
> + * Copyright 2017-2019 NXP
> */
Is there any problem to not add your name and Copyright?
>
> -#ifndef _ASM_ARCH_IMX8M_CLOCK_H
> -#define _ASM_ARCH_IMX8M_CLOCK_H
> -
> #include
>
> +#ifdef CONFIG_IMX8MQ
> +#include
> +#else
> +#error "Error no clock.h"
> +#endif
> +
> #define MHZ(X) ((X) * 100UL)
>
> -enum pll_clocks {
> - ANATOP_ARM_PLL,
> - ANATOP_GPU_PLL,
> - ANATOP_SYSTEM_PLL1,
> - ANATOP_SYSTEM_PLL2,
> - ANATOP_SYSTEM_PLL3,
> - ANATOP_AUDIO_PLL1,
> - ANATOP_AUDIO_PLL2,
> - ANATOP_VIDEO_PLL1,
> - ANATOP_VIDEO_PLL2,
> - ANATOP_DRAM_PLL,
> +/* Mainly for compatible to imx common code. */
> +enum mxc_clock {
> + MXC_ARM_CLK = 0,
> + MXC_IPG_CLK,
> + MXC_CSPI_CLK,
> + MXC_ESDHC_CLK,
> + MXC_ESDHC2_CLK,
> + MXC_ESDHC3_CLK,
> + MXC_I2C_CLK,
> + MXC_UART_CLK,
> + MXC_QSPI_CLK,
> };
>
> enum clk_slice_type {
> @@ -35,297 +36,6 @@ enum clk_slice_type {
> DRAM_SEL_CLOCK_SLICE,
> };
>
> -enum clk_root_index {
> - MXC_ARM_CLK = 0,
> - ARM_A53_CLK_ROOT= 0,
> - ARM_M4_CLK_ROOT = 1,
> - VPU_A53_CLK_ROOT= 2,
> - GPU_CORE_CLK_ROOT = 3,
> - GPU_SHADER_CLK_ROOT = 4,
> - MAIN_AXI_CLK_ROOT = 16,
> - ENET_AXI_CLK_ROOT = 17,
> - NAND_USDHC_BUS_CLK_ROOT = 18,
> - VPU_BUS_CLK_ROOT= 19,
> - DISPLAY_AXI_CLK_ROOT= 20,
> - DISPLAY_APB_CLK_ROOT= 21,
> - DISPLAY_RTRM_CLK_ROOT = 22,
> - USB_BUS_CLK_ROOT= 23,
> - GPU_AXI_CLK_ROOT= 24,
> - GPU_AHB_CLK_ROOT= 25,
> - NOC_CLK_ROOT= 26,
> - NOC_APB_CLK_ROOT= 27,
> - AHB_CLK_ROOT= 32,
> - IPG_CLK_ROOT= 33,
> - MXC_IPG_CLK = 33,
> - AUDIO_AHB_CLK_ROOT = 34,
> - MIPI_DSI_ESC_RX_CLK_ROOT= 36,
> - DRAM_SEL_CFG= 48,
> - CORE_SEL_CFG= 49,
> - DRAM_ALT_CLK_ROOT = 64,
> - DRAM_APB_CLK_ROOT = 65,
> - VPU_G1_CLK_ROOT = 66,
> - VPU_G2_CLK_ROOT = 67,
> - DISPLAY_DTRC_CLK_ROOT = 68,
> - DISPLAY_DC8000_CLK_ROOT = 69,
> - PCIE1_CTRL_CLK_ROOT = 70,
> - PCIE1_PHY_CLK_ROOT = 71,
> - PCIE1_AUX_CLK_ROOT = 72,
> - DC_PIXEL_CLK_ROOT = 73,
> - LCDIF_PIXEL_CLK_ROOT= 74,
> - SAI1_CLK_ROOT = 75,
> - SAI2_CLK_ROOT = 76,
> - SAI3_CLK_ROOT = 77,
> - SAI4_CLK_ROOT = 78,
> - SAI5_CLK_ROOT = 79,
> - SAI6_CLK_ROOT = 80,
> - SPDIF1_CLK_ROOT = 81,
> - SPDIF2_CLK_ROOT = 82,
> - ENET_REF_CLK_ROOT = 83,
> - ENET_TIMER_CLK_ROOT = 84,
> - ENET_PHY_REF_CLK_ROOT = 85,
> - NAND_CLK_ROOT = 86,
> - QSPI_CLK_ROOT = 87,
> - MXC_ESDHC_CLK = 88,
> - USDHC1_CLK_ROOT = 88,
> - MXC_ESDHC2_CLK = 89,
> - USDHC2_CLK_ROOT = 89,
> - I2C1_CLK_ROOT = 90,
> - MXC_I2C_CLK = 90,
> - I2C2_CLK_ROOT = 91,
> - I2C3_CLK_ROOT = 92,
> - I2C4_CLK_ROOT = 93,
> - UART1_CLK_ROOT = 94,
> - UART2_CLK_ROOT = 95,
> - UART3_CLK_ROOT = 96,
> - UART4_CLK_ROOT = 97,
> - USB_CORE_REF_CLK_ROOT = 98,
> - USB_PHY_REF_CLK_ROOT= 99,
> - GIC_CLK_ROOT= 100,
> - ECSPI1_CLK_ROOT = 101,
> -
[U-Boot] [PATCH 18/22] imx8m: restructure clock.h
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/clock.h| 491 +++--
arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 5 +-
3 files changed, 467 insertions(+), 453 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h
b/arch/arm/include/asm/arch-imx8m/clock.h
index e7c1670f6b..7225c760fe 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -1,28 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
- *
- * Peng Fan
+ * Copyright 2017-2019 NXP
*/
-#ifndef _ASM_ARCH_IMX8M_CLOCK_H
-#define _ASM_ARCH_IMX8M_CLOCK_H
-
#include
+#ifdef CONFIG_IMX8MQ
+#include
+#else
+#error "Error no clock.h"
+#endif
+
#define MHZ(X) ((X) * 100UL)
-enum pll_clocks {
- ANATOP_ARM_PLL,
- ANATOP_GPU_PLL,
- ANATOP_SYSTEM_PLL1,
- ANATOP_SYSTEM_PLL2,
- ANATOP_SYSTEM_PLL3,
- ANATOP_AUDIO_PLL1,
- ANATOP_AUDIO_PLL2,
- ANATOP_VIDEO_PLL1,
- ANATOP_VIDEO_PLL2,
- ANATOP_DRAM_PLL,
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+ MXC_UART_CLK,
+ MXC_QSPI_CLK,
};
enum clk_slice_type {
@@ -35,297 +36,6 @@ enum clk_slice_type {
DRAM_SEL_CLOCK_SLICE,
};
-enum clk_root_index {
- MXC_ARM_CLK = 0,
- ARM_A53_CLK_ROOT= 0,
- ARM_M4_CLK_ROOT = 1,
- VPU_A53_CLK_ROOT= 2,
- GPU_CORE_CLK_ROOT = 3,
- GPU_SHADER_CLK_ROOT = 4,
- MAIN_AXI_CLK_ROOT = 16,
- ENET_AXI_CLK_ROOT = 17,
- NAND_USDHC_BUS_CLK_ROOT = 18,
- VPU_BUS_CLK_ROOT= 19,
- DISPLAY_AXI_CLK_ROOT= 20,
- DISPLAY_APB_CLK_ROOT= 21,
- DISPLAY_RTRM_CLK_ROOT = 22,
- USB_BUS_CLK_ROOT= 23,
- GPU_AXI_CLK_ROOT= 24,
- GPU_AHB_CLK_ROOT= 25,
- NOC_CLK_ROOT= 26,
- NOC_APB_CLK_ROOT= 27,
- AHB_CLK_ROOT= 32,
- IPG_CLK_ROOT= 33,
- MXC_IPG_CLK = 33,
- AUDIO_AHB_CLK_ROOT = 34,
- MIPI_DSI_ESC_RX_CLK_ROOT= 36,
- DRAM_SEL_CFG= 48,
- CORE_SEL_CFG= 49,
- DRAM_ALT_CLK_ROOT = 64,
- DRAM_APB_CLK_ROOT = 65,
- VPU_G1_CLK_ROOT = 66,
- VPU_G2_CLK_ROOT = 67,
- DISPLAY_DTRC_CLK_ROOT = 68,
- DISPLAY_DC8000_CLK_ROOT = 69,
- PCIE1_CTRL_CLK_ROOT = 70,
- PCIE1_PHY_CLK_ROOT = 71,
- PCIE1_AUX_CLK_ROOT = 72,
- DC_PIXEL_CLK_ROOT = 73,
- LCDIF_PIXEL_CLK_ROOT= 74,
- SAI1_CLK_ROOT = 75,
- SAI2_CLK_ROOT = 76,
- SAI3_CLK_ROOT = 77,
- SAI4_CLK_ROOT = 78,
- SAI5_CLK_ROOT = 79,
- SAI6_CLK_ROOT = 80,
- SPDIF1_CLK_ROOT = 81,
- SPDIF2_CLK_ROOT = 82,
- ENET_REF_CLK_ROOT = 83,
- ENET_TIMER_CLK_ROOT = 84,
- ENET_PHY_REF_CLK_ROOT = 85,
- NAND_CLK_ROOT = 86,
- QSPI_CLK_ROOT = 87,
- MXC_ESDHC_CLK = 88,
- USDHC1_CLK_ROOT = 88,
- MXC_ESDHC2_CLK = 89,
- USDHC2_CLK_ROOT = 89,
- I2C1_CLK_ROOT = 90,
- MXC_I2C_CLK = 90,
- I2C2_CLK_ROOT = 91,
- I2C3_CLK_ROOT = 92,
- I2C4_CLK_ROOT = 93,
- UART1_CLK_ROOT = 94,
- UART2_CLK_ROOT = 95,
- UART3_CLK_ROOT = 96,
- UART4_CLK_ROOT = 97,
- USB_CORE_REF_CLK_ROOT = 98,
- USB_PHY_REF_CLK_ROOT= 99,
- GIC_CLK_ROOT= 100,
- ECSPI1_CLK_ROOT = 101,
- ECSPI2_CLK_ROOT = 102,
- PWM1_CLK_ROOT = 103,
- PWM2_CLK_ROOT = 104,
- PWM3_CLK_ROOT = 105,
- PWM4_CLK_ROOT
