The BCM283[56] contain both a L1 and L2 cache between the GPU (a/k/a
VideoCore CPU?) and DRAM. DMA-capable peripherals can also optionally
access DRAM via this same L2 cache (although they always bypass the L1
cache). Peripherals select whether to use or bypass the cache via the
top two bits of the bus address.
An IOMMU exists between the ARM CPU and the rest of the system. This
controls whether the ARM CPU's accesses use or bypass the L1 and/or L2
cache. This IOMMU is configured/controlled exclusively by the VideoCore
CPU.
In order for DRAM accesses made by the ARM core to be coherent with
accesses made by other DMA peripherals, we must program a bus address
into those peripherals that causes the peripheral's accesses to use the
same set of caches that the ARM core's accesses will use.
On the RPi1, the VideoCore firmware sets up the IOMMU to enable use of
the L2 cache. This corresponds to addresses based at 0x4000.
On the RPi2, the VideoCore firmware sets up the IOMMU to disable use of
the L2 cache. This corresponds to addresses based at 0xc000.
This patch implements U-Boot's phys_to_bus/bus_to_phys APIs according
to those rules.
For full details of this setup, please see Dom Cobley's description at:
http://lists.denx.de/pipermail/u-boot/2015-March/208201.html
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/215038
https://www.mail-archive.com/u-boot@lists.denx.de/msg166568.html
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
arch/arm/cpu/arm1176/bcm2835/Kconfig| 3 +++
arch/arm/cpu/arm1176/bcm2835/Makefile | 1 +
arch/arm/cpu/arm1176/bcm2835/phys2bus.c | 22 ++
arch/arm/cpu/armv7/bcm2835/Makefile | 1 +
4 files changed, 27 insertions(+)
create mode 100644 arch/arm/cpu/arm1176/bcm2835/phys2bus.c
diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig
b/arch/arm/cpu/arm1176/bcm2835/Kconfig
index 73cc72b41185..3181747fbfd7 100644
--- a/arch/arm/cpu/arm1176/bcm2835/Kconfig
+++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig
@@ -9,4 +9,7 @@ config DM_SERIAL
config DM_GPIO
default y
+config PHYS_TO_BUS
+ default y
+
endif
diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile
b/arch/arm/cpu/arm1176/bcm2835/Makefile
index 7e5dbe1fdeaf..6d1b74158773 100644
--- a/arch/arm/cpu/arm1176/bcm2835/Makefile
+++ b/arch/arm/cpu/arm1176/bcm2835/Makefile
@@ -6,3 +6,4 @@
obj-y := lowlevel_init.o
obj-y += init.o reset.o timer.o mbox.o
+obj-y += phys2bus.o
diff --git a/arch/arm/cpu/arm1176/bcm2835/phys2bus.c
b/arch/arm/cpu/arm1176/bcm2835/phys2bus.c
new file mode 100644
index ..fc1c29905de3
--- /dev/null
+++ b/arch/arm/cpu/arm1176/bcm2835/phys2bus.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2015 Stephen Warren
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include config.h
+#include phys2bus.h
+
+unsigned long phys_to_bus(unsigned long phys)
+{
+#ifdef CONFIG_BCM2836
+ return 0xc000 | phys;
+#else
+ return 0x4000 | phys;
+#endif
+}
+
+unsigned long bus_to_phys(unsigned long bus)
+{
+ return bus ~0xc000;
+}
diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile
b/arch/arm/cpu/armv7/bcm2835/Makefile
index ed1ee4753d49..5d14d8bdcac3 100644
--- a/arch/arm/cpu/armv7/bcm2835/Makefile
+++ b/arch/arm/cpu/armv7/bcm2835/Makefile
@@ -11,3 +11,4 @@ obj-y += $(src_dir)/init.o
obj-y += $(src_dir)/reset.o
obj-y += $(src_dir)/timer.o
obj-y += $(src_dir)/mbox.o
+obj-y += $(src_dir)/phys2bus.o
--
1.9.1
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