Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
Hi, Marek
sorry for possible format issue.
ср, 27 февр. 2019 г., 23:02 Marek Vasut :
> On 2/26/19 8:37 PM, Oleksandr wrote:
> >
> > Hi, Marek
>
> Hi,
>
> +}
> +
> +/*
> + * Reset vector for secondary CPUs.
> + * This will be mapped at address 0 by SBAR register.
> + * We need _long_ jump to the physical address.
> + */
> +asm(".arm\n"
> +".align 12\n"
> +".globl shmobile_boot_vector\n"
> +"shmobile_boot_vector:\n"
> +"ldr r1, 1f\n"
> +"bxr1\n"
> +".type shmobile_boot_vector, %function\n"
> +".size shmobile_boot_vector, .-shmobile_boot_vector\n"
> +".align2\n"
> +".globlshmobile_boot_fn\n"
> +"shmobile_boot_fn:\n"
> +"1:.space4\n"
> +".globlshmobile_boot_size\n"
> +"shmobile_boot_size:\n"
> +".long.-shmobile_boot_vector\n");
> >>> Why can't this be implemented in C ?
> >> This "reset vector" code was ported from Linux:
> >>
> >>
> https://elixir.bootlin.com/linux/v5.0-rc5/source/arch/arm/mach-shmobile/headsmp.S#L21
> >>
> >>
> >>
> >>
> >> Really don't know whether it can be implemented in C.
> >>
> >> I was thinking of moving this code to a separate ASM file in order
> >> not
> >> to mix C and ASM. What do you think about it?
> > U-Boot already has a reset vector code, can't that be reused ?
> I don't think. Being honest, I couldn't find an obvious way how to
> reuse
> (I assume you meant arch/arm/cpu/armv7/start.S).
> >>> Maybe it needs some additional work first ?
> >>> It seems Altera socfpga somehow uses the U-Boot reset vectors for PSCI,
> >>> so it should at least be possible.
> >>
> >> Could you, please, point me in code? Unfortunately, I wasn't able to
> >> find.
> >>
> >>
> >>>
> The newly turned on secondary CPU entry should be common
> "psci_cpu_entry", which does proper things.
>
> And this reset vector is just "a small piece of code" to be located in
> on-chip RAM (with limited size) and used for the jump stub...
> >>> We already have the SPL reset vectors in SRAM, maybe that can be
> >>> recycled somehow ?
> >>
> >>
> >> The only idea I have, how it may be recycled (not sure whether it will
> >> work...)
> >>
> >>
> >> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> >> index 0cb6dd39cc..69acf4677b 100644
> >> --- a/arch/arm/cpu/armv7/start.S
> >> +++ b/arch/arm/cpu/armv7/start.S
> >> @@ -36,6 +36,12 @@
> >> #endif
> >>
> >> reset:
> >> +
> >> +#if defined(CONFIG_ARMV7_PSCI) && !defined(CONFIG_SPL_BUILD)
> >> + b psci_cpu_entry_jump
> >> + /* return only if this is not "a newly turned on CPU" using
> >> PSCI) */
> >> +#endif
> >> +
> >> /* Allow the board to save important registers */
> >> b save_boot_params
> >> save_boot_params_ret:
> >> @@ -128,6 +134,21 @@ ENDPROC(switch_to_hypervisor)
> >> .weak switch_to_hypervisor
> >> #endif
> >>
> >> +/*
> >> + * Each platform which implements psci_cpu_entry_jump function should
> >> perform
> >> + * in the following way:
> >> + *
> >> + * If the executing this call CPU is exactly that CPU we are
> >> expecting to be
> >> + * powered on, then jump to psci_cpu_entry and never return.
> >> + * Otherwise return to the caller.
> >> + */
> >> +#if defined(CONFIG_ARMV7_PSCI) && !defined(CONFIG_SPL_BUILD)
> >> +ENTRY(psci_cpu_entry_jump)
> >> + movspc, lr
> >> +ENDPROC(psci_cpu_entry_jump)
> >> +.weak psci_cpu_entry_jump
> >> +#endif
> >> +
> >>
> /*
> >>
> >> *
> >> * cpu_init_cp15
> >>
> >>
> >> What do you think?
> >>
> >>
> >> It would be much appreciated, if you could provide some hints.
> >
> >
> > Don't want to be annoying, but it would be really nice to get my
> > questions answered...
>
> I am sorry, I am too busy right now. I will answer that once I can
> properly study the problem and give you a useful answer.
>
No problem, I will wait.
Thank you.
> --
> Best regards,
> Marek Vasut
>
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Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
On 2/26/19 8:37 PM, Oleksandr wrote:
>
> Hi, Marek
Hi,
+}
+
+/*
+ * Reset vector for secondary CPUs.
+ * This will be mapped at address 0 by SBAR register.
+ * We need _long_ jump to the physical address.
+ */
+asm(" .arm\n"
+ " .align 12\n"
+ " .globl shmobile_boot_vector\n"
+ "shmobile_boot_vector:\n"
+ " ldr r1, 1f\n"
+ " bx r1\n"
+ " .type shmobile_boot_vector, %function\n"
+ " .size shmobile_boot_vector, .-shmobile_boot_vector\n"
+ " .align 2\n"
+ " .globl shmobile_boot_fn\n"
+ "shmobile_boot_fn:\n"
+ "1: .space 4\n"
+ " .globl shmobile_boot_size\n"
+ "shmobile_boot_size:\n"
+ " .long .-shmobile_boot_vector\n");
>>> Why can't this be implemented in C ?
>> This "reset vector" code was ported from Linux:
>>
>> https://elixir.bootlin.com/linux/v5.0-rc5/source/arch/arm/mach-shmobile/headsmp.S#L21
>>
>>
>>
>>
>> Really don't know whether it can be implemented in C.
>>
>> I was thinking of moving this code to a separate ASM file in order
>> not
>> to mix C and ASM. What do you think about it?
> U-Boot already has a reset vector code, can't that be reused ?
I don't think. Being honest, I couldn't find an obvious way how to
reuse
(I assume you meant arch/arm/cpu/armv7/start.S).
>>> Maybe it needs some additional work first ?
>>> It seems Altera socfpga somehow uses the U-Boot reset vectors for PSCI,
>>> so it should at least be possible.
>>
>> Could you, please, point me in code? Unfortunately, I wasn't able to
>> find.
>>
>>
>>>
The newly turned on secondary CPU entry should be common
"psci_cpu_entry", which does proper things.
And this reset vector is just "a small piece of code" to be located in
on-chip RAM (with limited size) and used for the jump stub...
>>> We already have the SPL reset vectors in SRAM, maybe that can be
>>> recycled somehow ?
>>
>>
>> The only idea I have, how it may be recycled (not sure whether it will
>> work...)
>>
>>
>> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
>> index 0cb6dd39cc..69acf4677b 100644
>> --- a/arch/arm/cpu/armv7/start.S
>> +++ b/arch/arm/cpu/armv7/start.S
>> @@ -36,6 +36,12 @@
>> #endif
>>
>> reset:
>> +
>> +#if defined(CONFIG_ARMV7_PSCI) && !defined(CONFIG_SPL_BUILD)
>> + b psci_cpu_entry_jump
>> + /* return only if this is not "a newly turned on CPU" using
>> PSCI) */
>> +#endif
>> +
>> /* Allow the board to save important registers */
>> b save_boot_params
>> save_boot_params_ret:
>> @@ -128,6 +134,21 @@ ENDPROC(switch_to_hypervisor)
>> .weak switch_to_hypervisor
>> #endif
>>
>> +/*
>> + * Each platform which implements psci_cpu_entry_jump function should
>> perform
>> + * in the following way:
>> + *
>> + * If the executing this call CPU is exactly that CPU we are
>> expecting to be
>> + * powered on, then jump to psci_cpu_entry and never return.
>> + * Otherwise return to the caller.
>> + */
>> +#if defined(CONFIG_ARMV7_PSCI) && !defined(CONFIG_SPL_BUILD)
>> +ENTRY(psci_cpu_entry_jump)
>> + movs pc, lr
>> +ENDPROC(psci_cpu_entry_jump)
>> +.weak psci_cpu_entry_jump
>> +#endif
>> +
>> /*
>>
>> *
>> * cpu_init_cp15
>>
>>
>> What do you think?
>>
>>
>> It would be much appreciated, if you could provide some hints.
>
>
> Don't want to be annoying, but it would be really nice to get my
> questions answered...
I am sorry, I am too busy right now. I will answer that once I can
properly study the problem and give you a useful answer.
--
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
Hi, Marek
+}
+
+/*
+ * Reset vector for secondary CPUs.
+ * This will be mapped at address 0 by SBAR register.
+ * We need _long_ jump to the physical address.
+ */
+asm(" .arm\n"
+ " .align 12\n"
+ " .globl shmobile_boot_vector\n"
+ "shmobile_boot_vector:\n"
+ " ldr r1, 1f\n"
+ " bx r1\n"
+ " .type shmobile_boot_vector, %function\n"
+ " .size shmobile_boot_vector, .-shmobile_boot_vector\n"
+ " .align 2\n"
+ " .globl shmobile_boot_fn\n"
+ "shmobile_boot_fn:\n"
+ "1: .space 4\n"
+ " .globl shmobile_boot_size\n"
+ "shmobile_boot_size:\n"
+ " .long .-shmobile_boot_vector\n");
Why can't this be implemented in C ?
This "reset vector" code was ported from Linux:
https://elixir.bootlin.com/linux/v5.0-rc5/source/arch/arm/mach-shmobile/headsmp.S#L21
Really don't know whether it can be implemented in C.
I was thinking of moving this code to a separate ASM file in order
not
to mix C and ASM. What do you think about it?
U-Boot already has a reset vector code, can't that be reused ?
I don't think. Being honest, I couldn't find an obvious way how to
reuse
(I assume you meant arch/arm/cpu/armv7/start.S).
Maybe it needs some additional work first ?
It seems Altera socfpga somehow uses the U-Boot reset vectors for PSCI,
so it should at least be possible.
Could you, please, point me in code? Unfortunately, I wasn't able to
find.
The newly turned on secondary CPU entry should be common
"psci_cpu_entry", which does proper things.
And this reset vector is just "a small piece of code" to be located in
on-chip RAM (with limited size) and used for the jump stub...
We already have the SPL reset vectors in SRAM, maybe that can be
recycled somehow ?
The only idea I have, how it may be recycled (not sure whether it will
work...)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0cb6dd39cc..69acf4677b 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -36,6 +36,12 @@
#endif
reset:
+
+#if defined(CONFIG_ARMV7_PSCI) && !defined(CONFIG_SPL_BUILD)
+ b psci_cpu_entry_jump
+ /* return only if this is not "a newly turned on CPU" using
PSCI) */
+#endif
+
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
@@ -128,6 +134,21 @@ ENDPROC(switch_to_hypervisor)
.weak switch_to_hypervisor
#endif
+/*
+ * Each platform which implements psci_cpu_entry_jump function should
perform
+ * in the following way:
+ *
+ * If the executing this call CPU is exactly that CPU we are
expecting to be
+ * powered on, then jump to psci_cpu_entry and never return.
+ * Otherwise return to the caller.
+ */
+#if defined(CONFIG_ARMV7_PSCI) && !defined(CONFIG_SPL_BUILD)
+ENTRY(psci_cpu_entry_jump)
+ movs pc, lr
+ENDPROC(psci_cpu_entry_jump)
+.weak psci_cpu_entry_jump
+#endif
+
/*
*
* cpu_init_cp15
What do you think?
It would be much appreciated, if you could provide some hints.
Don't want to be annoying, but it would be really nice to get my
questions answered...
--
Regards,
Oleksandr Tyshchenko
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Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
On 11.02.19 22:40, Marek Vasut wrote:
Hi
On 2/11/19 9:10 PM, Oleksandr wrote:
[...]
Yes. I had to re-implement. Let me describe why.
From my understanding (I may mistake), the PSCI backend code which
lives
in secure section should be as lightweight as possible
and shouldn't call any U-Boot routines not marked as __secure, except
simple static inline functions.
You can see PSCI implementation for any platform in U-Boot, and only
simple "macroses/inlines" are used across all of them.
Even for realizing some delay in code, they have specially implemented
something simple. As an example __mdelay() realization here:
https://elixir.bootlin.com/u-boot/v2019.01/source/arch/arm/cpu/armv7/sunxi/psci.c#L61
Can the U-Boot code be refactored somehow to avoid the duplication ?
Sorry, what duplication you are speaking about?
It is my impression that we're reimplementing code we already have
either in drivers/ or in Linux, again, in arch/arm/ . Isn't it the case ?
All this code (for preparing, powering up/down the CPUs and related
peripherals) which this patch introduces, is new for U-Boot.
But, yes, it is present in Linux (arch/arm/mach-shmobile/...).
I know that PMIC (for Lager) and CPLD (for Stout) assist SoC to perform
reset. But, I couldn't use that functional here in PSCI backend, as it
pulls a lot of code (i2c for PMIC, gpio manipulation for CPLD, etc),
How can the reset work properly if the CPLD/PMIC isn't even used then ?
We ask WDT to perform a CPU reset, although this is not the same reset
as an external reset from CPLD/PMIC,
but, why not use it, if we don't have alternative? This is certainly
better than nothing, I think.
Do we need to do a full board reset in this case ?
After WDT reset CPU will be brought up to bootrom code, then starts
executing SPL, U-Boot...
So, we will get all required SoC/Board peripherals re-initialized, I think.
Actually, we ask WDT to do what it is intended to do, and it seems to
work properly as the system up and running after WDT reset in 100% cases.
What is more, this PSCI reset implementation could be common for Gen2
SoCs where WDT is present...
so for that reason (AFAIK the PSCI system reset is a mandatory option) I
chose WDT as a entity for doing a reset. This is quite simple and can be
used on both boards, what is more that it can be used on other Gen2 SoC
if required.
+}
+
+/*
+ * Functions which intended to be called from PSCI board
initialization.
+
*/
+static int sysc_power_up(int scu)
+{
+ u32 status, chan_offs, isr_bit;
+ int i, j, ret = 0;
+
+ if (scu == CA15_SCU) {
+ chan_offs = CA15_SCU_CHAN_OFFS;
+ isr_bit = CA15_SCU_ISR_BIT;
+ } else {
+ chan_offs = CA7_SCU_CHAN_OFFS;
+ isr_bit = CA7_SCU_ISR_BIT;
+ }
+
+ writel(BIT(isr_bit), SYSC_BASE + SYSCISCR);
+
+ /* Submit power resume request until it was accepted */
+ for (i = 0; i < PWRER_RETRIES; i++) {
+ /* Wait until SYSC is ready to accept a power resume
request */
+ for (j = 0; j < SYSCSR_RETRIES; j++) {
+ if (readl(SYSC_BASE + SYSCSR) & BIT(1))
+ break;
+
+ udelay(SYSCSR_DELAY_US);
+ }
+
+ if (j == SYSCSR_RETRIES)
+ return -EAGAIN;
+
+ /* Submit power resume request */
+ writel(BIT(0), SYSC_BASE + chan_offs + PWRONCR_OFFS);
+
+ /* Check if power resume request was accepted */
+ status = readl(SYSC_BASE + chan_offs + PWRER_OFFS);
+ if (!(status & BIT(0)))
+ break;
+
+ udelay(PWRER_DELAY_US);
+ }
+
+ if (i == PWRER_RETRIES)
+ return -EIO;
+
+ /* Wait until the power resume request has completed */
+ for (i = 0; i < SYSCISR_RETRIES; i++) {
+ if (readl(SYSC_BASE + SYSCISR) & BIT(isr_bit))
+ break;
+ udelay(SYSCISR_DELAY_US);
+ }
+
+ if (i == SYSCISR_RETRIES)
+ ret = -EIO;
+
+ writel(BIT(isr_bit), SYSC_BASE + SYSCISCR);
+
+ return ret;
+}
+
+static bool sysc_power_is_off(int scu)
+{
+ u32 status, chan_offs;
+
+ chan_offs = scu == CA15_SCU ? CA15_SCU_CHAN_OFFS :
CA7_SCU_CHAN_OFFS;
+
+ /* Check if SCU is in power shutoff state */
+ status = readl(SYSC_BASE + chan_offs + PWRSR_OFFS);
+ if (status & BIT(0))
+ return true;
+
+ return false;
+}
+
+static void apmu_setup_debug_mode(int cpu)
+{
+ int cluster = r8a7790_cluster_id(cpu);
+ u32 apmu_base, reg;
+
+ apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
+
+ /*
+ * Enable reset requests derived from power shutoff to the
AP-system
+ * CPU cores in debug mode. Without taking care of, they may
fail to
+ * resume from the power shutoff state.
+ */
+ reg = readl(apmu_base + DBGRCR_OFFS);
+ reg |= DBGCPUREN | DBGCPUNREN(r8a7790_core_id(cpu)) | DBGCPUPREN;
+ writel(reg,
Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
On 2/11/19 9:10 PM, Oleksandr wrote:
[...]
>>> Yes. I had to re-implement. Let me describe why.
>>>
>>> From my understanding (I may mistake), the PSCI backend code which
>>> lives
>>> in secure section should be as lightweight as possible
>>>
>>> and shouldn't call any U-Boot routines not marked as __secure, except
>>> simple static inline functions.
>>>
>>> You can see PSCI implementation for any platform in U-Boot, and only
>>> simple "macroses/inlines" are used across all of them.
>>>
>>> Even for realizing some delay in code, they have specially implemented
>>> something simple. As an example __mdelay() realization here:
>>>
>>> https://elixir.bootlin.com/u-boot/v2019.01/source/arch/arm/cpu/armv7/sunxi/psci.c#L61
>>>
>> Can the U-Boot code be refactored somehow to avoid the duplication ?
>
> Sorry, what duplication you are speaking about?
It is my impression that we're reimplementing code we already have
either in drivers/ or in Linux, again, in arch/arm/ . Isn't it the case ?
>>> I know that PMIC (for Lager) and CPLD (for Stout) assist SoC to perform
>>> reset. But, I couldn't use that functional here in PSCI backend, as it
>>> pulls a lot of code (i2c for PMIC, gpio manipulation for CPLD, etc),
>> How can the reset work properly if the CPLD/PMIC isn't even used then ?
>
>
> We ask WDT to perform a CPU reset, although this is not the same reset
> as an external reset from CPLD/PMIC,
>
> but, why not use it, if we don't have alternative? This is certainly
> better than nothing, I think.
Do we need to do a full board reset in this case ?
> Actually, we ask WDT to do what it is intended to do, and it seems to
> work properly as the system up and running after WDT reset in 100% cases.
>
> What is more, this PSCI reset implementation could be common for Gen2
> SoCs where WDT is present...
>
>
>>> so for that reason (AFAIK the PSCI system reset is a mandatory option) I
>>> chose WDT as a entity for doing a reset. This is quite simple and can be
>>> used on both boards, what is more that it can be used on other Gen2 SoC
>>> if required.
>>>
> +}
> +
> +/*
>
>
> + * Functions which intended to be called from PSCI board
> initialization.
> +
> */
>
>
> +static int sysc_power_up(int scu)
> +{
> + u32 status, chan_offs, isr_bit;
> + int i, j, ret = 0;
> +
> + if (scu == CA15_SCU) {
> + chan_offs = CA15_SCU_CHAN_OFFS;
> + isr_bit = CA15_SCU_ISR_BIT;
> + } else {
> + chan_offs = CA7_SCU_CHAN_OFFS;
> + isr_bit = CA7_SCU_ISR_BIT;
> + }
> +
> + writel(BIT(isr_bit), SYSC_BASE + SYSCISCR);
> +
> + /* Submit power resume request until it was accepted */
> + for (i = 0; i < PWRER_RETRIES; i++) {
> + /* Wait until SYSC is ready to accept a power resume
> request */
> + for (j = 0; j < SYSCSR_RETRIES; j++) {
> + if (readl(SYSC_BASE + SYSCSR) & BIT(1))
> + break;
> +
> + udelay(SYSCSR_DELAY_US);
> + }
> +
> + if (j == SYSCSR_RETRIES)
> + return -EAGAIN;
> +
> + /* Submit power resume request */
> + writel(BIT(0), SYSC_BASE + chan_offs + PWRONCR_OFFS);
> +
> + /* Check if power resume request was accepted */
> + status = readl(SYSC_BASE + chan_offs + PWRER_OFFS);
> + if (!(status & BIT(0)))
> + break;
> +
> + udelay(PWRER_DELAY_US);
> + }
> +
> + if (i == PWRER_RETRIES)
> + return -EIO;
> +
> + /* Wait until the power resume request has completed */
> + for (i = 0; i < SYSCISR_RETRIES; i++) {
> + if (readl(SYSC_BASE + SYSCISR) & BIT(isr_bit))
> + break;
> + udelay(SYSCISR_DELAY_US);
> + }
> +
> + if (i == SYSCISR_RETRIES)
> + ret = -EIO;
> +
> + writel(BIT(isr_bit), SYSC_BASE + SYSCISCR);
> +
> + return ret;
> +}
> +
> +static bool sysc_power_is_off(int scu)
> +{
> + u32 status, chan_offs;
> +
> + chan_offs = scu == CA15_SCU ? CA15_SCU_CHAN_OFFS :
> CA7_SCU_CHAN_OFFS;
> +
> + /* Check if SCU is in power shutoff state */
> + status = readl(SYSC_BASE + chan_offs + PWRSR_OFFS);
> + if (status & BIT(0))
> + return true;
> +
> + return false;
> +}
> +
> +static void apmu_setup_debug_mode(int cpu)
> +{
> + int cluster = r8a7790_cluster_id(cpu);
> + u32 apmu_base, reg;
> +
> + apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
> +
> + /*
> + * Enable reset requests derived from power shutoff to the
> AP-system
Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
On 09.02.19 18:32, Marek Vasut wrote:
On 2/8/19 11:52 AM, Oleksandr wrote:
On 05.02.19 20:55, Marek Vasut wrote:
Hi Marek
Hi,
Hi Marek
On 1/31/19 6:38 PM, Oleksandr Tyshchenko wrote:
From: Oleksandr Tyshchenko
Also enable PSCI support for Stout and Lager boards where
actually the r8a7790 SoC is installed.
All secondary CPUs will be switched to a non-secure HYP mode
after booting.
Signed-off-by: Oleksandr Tyshchenko
---
arch/arm/mach-rmobile/Kconfig.32 | 2 +
arch/arm/mach-rmobile/Makefile | 6 +
arch/arm/mach-rmobile/pm-r8a7790.c | 408
+
arch/arm/mach-rmobile/pm-r8a7790.h | 72 +++
arch/arm/mach-rmobile/psci.c | 193 ++
include/configs/lager.h | 2 +
include/configs/stout.h | 2 +
7 files changed, 685 insertions(+)
create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.c
create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.h
create mode 100644 arch/arm/mach-rmobile/psci.c
diff --git a/arch/arm/mach-rmobile/Kconfig.32
b/arch/arm/mach-rmobile/Kconfig.32
index a2e9e3d..728c323 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -78,6 +78,7 @@ config TARGET_LAGER
imply CMD_DM
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
config TARGET_KZM9G
bool "KZM9D board"
@@ -119,6 +120,7 @@ config TARGET_STOUT
imply CMD_DM
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
To myself: Move this option under "config R8A7790".
endchoice
diff --git a/arch/arm/mach-rmobile/Makefile
b/arch/arm/mach-rmobile/Makefile
index 1f26ada..6f4c513 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,3 +13,9 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o
cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o
pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o
memmap-gen3.o
+
+ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_R8A7790
+obj-$(CONFIG_ARMV7_PSCI) += psci.o pm-r8a7790.o
+endif
+endif
diff --git a/arch/arm/mach-rmobile/pm-r8a7790.c
b/arch/arm/mach-rmobile/pm-r8a7790.c
new file mode 100644
index 000..c635cf6
--- /dev/null
+++ b/arch/arm/mach-rmobile/pm-r8a7790.c
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPU power management support for Renesas r8a7790 SoC
+ *
+ * Contains functions to control ARM Cortex A15/A7 cores and
+ * related peripherals basically used for PSCI.
+ *
+ * Copyright (C) 2018 EPAM Systems Inc.
+ *
+ * Mainly based on Renesas R-Car Gen2 platform code from Linux:
+ * arch/arm/mach-shmobile/...
+ */
+
+#include
+#include
+#include
+
+#include "pm-r8a7790.h"
+
+/*
I'd expect checkpatch to complain about these long lines of asterisks.
No, there was no complain about it. I have checked. Anyway, I can remove
them if required.
Yes please, keep the comment style consistent with the rest of the
codebase, which is also the kernel comment style.
OK, will remove
+ * APMU definitions
+
*/
+#define CA15_APMU_BASE 0xe6152000
+#define CA7_APMU_BASE 0xe6151000
All these addresses should come from DT. And the driver should be DM
capable and live in drivers/
[...]
All PSCI backends for ARMV7 in U-Boot which I was able to found, are
located either in arch/arm/cpu/armv7/
or in arch/arm/mach-X. As well as other PSCI backends, this one will be
located in a separate secure section and acts as secure monitor,
so it will be still alive, when U-Boot is gone away. Do we really want
this one to go into drivers?
I'd much prefer it if we stopped adding more stuff to arch/arm/mach-* ,
but I think we cannot avoid that in this case, can we ?
I am afraid, we can't avoid.
+/*
+ * Functions which intended to be called from PSCI handlers. These
functions
+ * marked as __secure and are placed in .secure section.
+
*/
+void __secure r8a7790_apmu_power_on(int cpu)
+{
+ int cluster = r8a7790_cluster_id(cpu);
+ u32 apmu_base;
+
+ apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
+
+ /* Request power on */
+ writel(BIT(r8a7790_core_id(cpu)), apmu_base + WUPCR_OFFS);
wait_for_bit of some sorts ?
probably yes, will re-use
+ /* Wait for APMU to finish */
+ while (readl(apmu_base + WUPCR_OFFS))
+ ;
Can this spin forever ?
I didn't find anything in TRM which describes how long it may take.
Linux also doesn't use timeout.
https://elixir.bootlin.com/linux/v5.0-rc5/source/arch/arm/mach-shmobile/platsmp-apmu.c#L46
Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
On 2/8/19 11:52 AM, Oleksandr wrote:
>
> On 05.02.19 20:55, Marek Vasut wrote:
>
> Hi Marek
Hi,
>> On 1/31/19 6:38 PM, Oleksandr Tyshchenko wrote:
>>> From: Oleksandr Tyshchenko
>>>
>>> Also enable PSCI support for Stout and Lager boards where
>>> actually the r8a7790 SoC is installed.
>>>
>>> All secondary CPUs will be switched to a non-secure HYP mode
>>> after booting.
>>>
>>> Signed-off-by: Oleksandr Tyshchenko
>>> ---
>>> arch/arm/mach-rmobile/Kconfig.32 | 2 +
>>> arch/arm/mach-rmobile/Makefile | 6 +
>>> arch/arm/mach-rmobile/pm-r8a7790.c | 408
>>> +
>>> arch/arm/mach-rmobile/pm-r8a7790.h | 72 +++
>>> arch/arm/mach-rmobile/psci.c | 193 ++
>>> include/configs/lager.h | 2 +
>>> include/configs/stout.h | 2 +
>>> 7 files changed, 685 insertions(+)
>>> create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.c
>>> create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.h
>>> create mode 100644 arch/arm/mach-rmobile/psci.c
>>>
>>> diff --git a/arch/arm/mach-rmobile/Kconfig.32
>>> b/arch/arm/mach-rmobile/Kconfig.32
>>> index a2e9e3d..728c323 100644
>>> --- a/arch/arm/mach-rmobile/Kconfig.32
>>> +++ b/arch/arm/mach-rmobile/Kconfig.32
>>> @@ -78,6 +78,7 @@ config TARGET_LAGER
>>> imply CMD_DM
>>> select CPU_V7_HAS_NONSEC
>>> select CPU_V7_HAS_VIRT
>>> + select ARCH_SUPPORT_PSCI
>>> config TARGET_KZM9G
>>> bool "KZM9D board"
>>> @@ -119,6 +120,7 @@ config TARGET_STOUT
>>> imply CMD_DM
>>> select CPU_V7_HAS_NONSEC
>>> select CPU_V7_HAS_VIRT
>>> + select ARCH_SUPPORT_PSCI
>
> To myself: Move this option under "config R8A7790".
>
>>> endchoice
>>> diff --git a/arch/arm/mach-rmobile/Makefile
>>> b/arch/arm/mach-rmobile/Makefile
>>> index 1f26ada..6f4c513 100644
>>> --- a/arch/arm/mach-rmobile/Makefile
>>> +++ b/arch/arm/mach-rmobile/Makefile
>>> @@ -13,3 +13,9 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o
>>> cpu_info-sh73a0.o pfc-sh73a0.o
>>> obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o
>>> pfc-r8a7740.o
>>> obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
>>> obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o
>>> memmap-gen3.o
>>> +
>>> +ifndef CONFIG_SPL_BUILD
>>> +ifdef CONFIG_R8A7790
>>> +obj-$(CONFIG_ARMV7_PSCI) += psci.o pm-r8a7790.o
>>> +endif
>>> +endif
>>> diff --git a/arch/arm/mach-rmobile/pm-r8a7790.c
>>> b/arch/arm/mach-rmobile/pm-r8a7790.c
>>> new file mode 100644
>>> index 000..c635cf6
>>> --- /dev/null
>>> +++ b/arch/arm/mach-rmobile/pm-r8a7790.c
>>> @@ -0,0 +1,408 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * CPU power management support for Renesas r8a7790 SoC
>>> + *
>>> + * Contains functions to control ARM Cortex A15/A7 cores and
>>> + * related peripherals basically used for PSCI.
>>> + *
>>> + * Copyright (C) 2018 EPAM Systems Inc.
>>> + *
>>> + * Mainly based on Renesas R-Car Gen2 platform code from Linux:
>>> + * arch/arm/mach-shmobile/...
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +#include "pm-r8a7790.h"
>>> +
>>> +/*
>>>
>> I'd expect checkpatch to complain about these long lines of asterisks.
>
> No, there was no complain about it. I have checked. Anyway, I can remove
> them if required.
Yes please, keep the comment style consistent with the rest of the
codebase, which is also the kernel comment style.
>>> + * APMU definitions
>>> +
>>> */
>>>
>>> +#define CA15_APMU_BASE 0xe6152000
>>> +#define CA7_APMU_BASE 0xe6151000
>> All these addresses should come from DT. And the driver should be DM
>> capable and live in drivers/
>>
>> [...]
>
> All PSCI backends for ARMV7 in U-Boot which I was able to found, are
> located either in arch/arm/cpu/armv7/
>
> or in arch/arm/mach-X. As well as other PSCI backends, this one will be
> located in a separate secure section and acts as secure monitor,
>
> so it will be still alive, when U-Boot is gone away. Do we really want
> this one to go into drivers?
I'd much prefer it if we stopped adding more stuff to arch/arm/mach-* ,
but I think we cannot avoid that in this case, can we ?
>>> +/*
>>>
>>> + * Functions which intended to be called from PSCI handlers. These
>>> functions
>>> + * marked as __secure and are placed in .secure section.
>>> +
>>> */
>>>
>>> +void __secure r8a7790_apmu_power_on(int cpu)
>>> +{
>>> + int cluster = r8a7790_cluster_id(cpu);
>>> + u32 apmu_base;
>>> +
>>> + apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
>>> +
>>> + /* Request power on */
>>> + writel(BIT(r8a7790_core_id(cpu)), apmu_base + WUPCR_OFFS);
>> wait_for_bit
Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
On 05.02.19 20:55, Marek Vasut wrote:
Hi Marek
On 1/31/19 6:38 PM, Oleksandr Tyshchenko wrote:
From: Oleksandr Tyshchenko
Also enable PSCI support for Stout and Lager boards where
actually the r8a7790 SoC is installed.
All secondary CPUs will be switched to a non-secure HYP mode
after booting.
Signed-off-by: Oleksandr Tyshchenko
---
arch/arm/mach-rmobile/Kconfig.32 | 2 +
arch/arm/mach-rmobile/Makefile | 6 +
arch/arm/mach-rmobile/pm-r8a7790.c | 408 +
arch/arm/mach-rmobile/pm-r8a7790.h | 72 +++
arch/arm/mach-rmobile/psci.c | 193 ++
include/configs/lager.h| 2 +
include/configs/stout.h| 2 +
7 files changed, 685 insertions(+)
create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.c
create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.h
create mode 100644 arch/arm/mach-rmobile/psci.c
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index a2e9e3d..728c323 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -78,6 +78,7 @@ config TARGET_LAGER
imply CMD_DM
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
config TARGET_KZM9G
bool "KZM9D board"
@@ -119,6 +120,7 @@ config TARGET_STOUT
imply CMD_DM
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
To myself: Move this option under "config R8A7790".
endchoice
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 1f26ada..6f4c513 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,3 +13,9 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o
pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+
+ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_R8A7790
+obj-$(CONFIG_ARMV7_PSCI) += psci.o pm-r8a7790.o
+endif
+endif
diff --git a/arch/arm/mach-rmobile/pm-r8a7790.c
b/arch/arm/mach-rmobile/pm-r8a7790.c
new file mode 100644
index 000..c635cf6
--- /dev/null
+++ b/arch/arm/mach-rmobile/pm-r8a7790.c
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CPU power management support for Renesas r8a7790 SoC
+ *
+ * Contains functions to control ARM Cortex A15/A7 cores and
+ * related peripherals basically used for PSCI.
+ *
+ * Copyright (C) 2018 EPAM Systems Inc.
+ *
+ * Mainly based on Renesas R-Car Gen2 platform code from Linux:
+ *arch/arm/mach-shmobile/...
+ */
+
+#include
+#include
+#include
+
+#include "pm-r8a7790.h"
+
+/*
I'd expect checkpatch to complain about these long lines of asterisks.
No, there was no complain about it. I have checked. Anyway, I can remove
them if required.
+ * APMU definitions
+ */
+#define CA15_APMU_BASE 0xe6152000
+#define CA7_APMU_BASE 0xe6151000
All these addresses should come from DT. And the driver should be DM
capable and live in drivers/
[...]
All PSCI backends for ARMV7 in U-Boot which I was able to found, are
located either in arch/arm/cpu/armv7/
or in arch/arm/mach-X. As well as other PSCI backends, this one will be
located in a separate secure section and acts as secure monitor,
so it will be still alive, when U-Boot is gone away. Do we really want
this one to go into drivers?
+/*
+ * Functions which intended to be called from PSCI handlers. These functions
+ * marked as __secure and are placed in .secure section.
+ */
+void __secure r8a7790_apmu_power_on(int cpu)
+{
+ int cluster = r8a7790_cluster_id(cpu);
+ u32 apmu_base;
+
+ apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
+
+ /* Request power on */
+ writel(BIT(r8a7790_core_id(cpu)), apmu_base + WUPCR_OFFS);
wait_for_bit of some sorts ?
probably yes, will re-use
+ /* Wait for APMU to finish */
+ while (readl(apmu_base + WUPCR_OFFS))
+ ;
Can this spin forever ?
I didn't find anything in TRM which describes how long it may take.
Linux also doesn't use timeout.
https://elixir.bootlin.com/linux/v5.0-rc5/source/arch/arm/mach-shmobile/platsmp-apmu.c#L46
Shall I add some timeout (probably 1s) in order to be completely safe?
+}
+
+void __secure r8a7790_apmu_power_off(int cpu)
+{
+ int cluster = r8a7790_cluster_id(cpu);
+ u32 apmu_base;
+
+ apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
+
+ /* Request Core Standby for next WFI */
+ writel(CPUPWR_STANDBY, apmu_base +
Re: [U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
On 1/31/19 6:38 PM, Oleksandr Tyshchenko wrote:
> From: Oleksandr Tyshchenko
>
> Also enable PSCI support for Stout and Lager boards where
> actually the r8a7790 SoC is installed.
>
> All secondary CPUs will be switched to a non-secure HYP mode
> after booting.
>
> Signed-off-by: Oleksandr Tyshchenko
> ---
> arch/arm/mach-rmobile/Kconfig.32 | 2 +
> arch/arm/mach-rmobile/Makefile | 6 +
> arch/arm/mach-rmobile/pm-r8a7790.c | 408
> +
> arch/arm/mach-rmobile/pm-r8a7790.h | 72 +++
> arch/arm/mach-rmobile/psci.c | 193 ++
> include/configs/lager.h| 2 +
> include/configs/stout.h| 2 +
> 7 files changed, 685 insertions(+)
> create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.c
> create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.h
> create mode 100644 arch/arm/mach-rmobile/psci.c
>
> diff --git a/arch/arm/mach-rmobile/Kconfig.32
> b/arch/arm/mach-rmobile/Kconfig.32
> index a2e9e3d..728c323 100644
> --- a/arch/arm/mach-rmobile/Kconfig.32
> +++ b/arch/arm/mach-rmobile/Kconfig.32
> @@ -78,6 +78,7 @@ config TARGET_LAGER
> imply CMD_DM
> select CPU_V7_HAS_NONSEC
> select CPU_V7_HAS_VIRT
> + select ARCH_SUPPORT_PSCI
>
> config TARGET_KZM9G
> bool "KZM9D board"
> @@ -119,6 +120,7 @@ config TARGET_STOUT
> imply CMD_DM
> select CPU_V7_HAS_NONSEC
> select CPU_V7_HAS_VIRT
> + select ARCH_SUPPORT_PSCI
>
> endchoice
>
> diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
> index 1f26ada..6f4c513 100644
> --- a/arch/arm/mach-rmobile/Makefile
> +++ b/arch/arm/mach-rmobile/Makefile
> @@ -13,3 +13,9 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o
> pfc-sh73a0.o
> obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
> obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
> obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
> +
> +ifndef CONFIG_SPL_BUILD
> +ifdef CONFIG_R8A7790
> +obj-$(CONFIG_ARMV7_PSCI) += psci.o pm-r8a7790.o
> +endif
> +endif
> diff --git a/arch/arm/mach-rmobile/pm-r8a7790.c
> b/arch/arm/mach-rmobile/pm-r8a7790.c
> new file mode 100644
> index 000..c635cf6
> --- /dev/null
> +++ b/arch/arm/mach-rmobile/pm-r8a7790.c
> @@ -0,0 +1,408 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * CPU power management support for Renesas r8a7790 SoC
> + *
> + * Contains functions to control ARM Cortex A15/A7 cores and
> + * related peripherals basically used for PSCI.
> + *
> + * Copyright (C) 2018 EPAM Systems Inc.
> + *
> + * Mainly based on Renesas R-Car Gen2 platform code from Linux:
> + *arch/arm/mach-shmobile/...
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include "pm-r8a7790.h"
> +
> +/*
I'd expect checkpatch to complain about these long lines of asterisks.
> + * APMU definitions
> +
> */
> +#define CA15_APMU_BASE 0xe6152000
> +#define CA7_APMU_BASE0xe6151000
All these addresses should come from DT. And the driver should be DM
capable and live in drivers/
[...]
> +/*
> + * Functions which intended to be called from PSCI handlers. These functions
> + * marked as __secure and are placed in .secure section.
> +
> */
> +void __secure r8a7790_apmu_power_on(int cpu)
> +{
> + int cluster = r8a7790_cluster_id(cpu);
> + u32 apmu_base;
> +
> + apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
> +
> + /* Request power on */
> + writel(BIT(r8a7790_core_id(cpu)), apmu_base + WUPCR_OFFS);
wait_for_bit of some sorts ?
> + /* Wait for APMU to finish */
> + while (readl(apmu_base + WUPCR_OFFS))
> + ;
Can this spin forever ?
> +}
> +
> +void __secure r8a7790_apmu_power_off(int cpu)
> +{
> + int cluster = r8a7790_cluster_id(cpu);
> + u32 apmu_base;
> +
> + apmu_base = cluster == 0 ? CA15_APMU_BASE : CA7_APMU_BASE;
> +
> + /* Request Core Standby for next WFI */
> + writel(CPUPWR_STANDBY, apmu_base + CPUNCR_OFFS(r8a7790_core_id(cpu)));
> +}
> +
> +void __secure r8a7790_assert_reset(int cpu)
> +{
> + int cluster = r8a7790_cluster_id(cpu);
> + u32 mask, magic, rescnt;
> +
> + mask = BIT(3 - r8a7790_core_id(cpu));
> + magic = cluster == 0 ? CA15RESCNT_CODE : CA7RESCNT_CODE;
> + rescnt = RST_BASE + (cluster == 0 ? CA15RESCNT : CA7RESCNT);
> + writel((readl(rescnt) | mask) | magic, rescnt);
> +}
> +
> +void __secure r8a7790_deassert_reset(int cpu)
> +{
> + int cluster = r8a7790_cluster_id(cpu);
> + u32 mask, magic, rescnt;
> +
> + mask = BIT(3 - r8a7790_core_id(cpu));
> + magic = cluster == 0 ? CA15RESCNT_CODE :
[U-Boot] [PATCH 2/3] ARM: rmobile: Add basic PSCI support for r8a7790 SoC
From: Oleksandr Tyshchenko Also enable PSCI support for Stout and Lager boards where actually the r8a7790 SoC is installed. All secondary CPUs will be switched to a non-secure HYP mode after booting. Signed-off-by: Oleksandr Tyshchenko --- arch/arm/mach-rmobile/Kconfig.32 | 2 + arch/arm/mach-rmobile/Makefile | 6 + arch/arm/mach-rmobile/pm-r8a7790.c | 408 + arch/arm/mach-rmobile/pm-r8a7790.h | 72 +++ arch/arm/mach-rmobile/psci.c | 193 ++ include/configs/lager.h| 2 + include/configs/stout.h| 2 + 7 files changed, 685 insertions(+) create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.c create mode 100644 arch/arm/mach-rmobile/pm-r8a7790.h create mode 100644 arch/arm/mach-rmobile/psci.c diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index a2e9e3d..728c323 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -78,6 +78,7 @@ config TARGET_LAGER imply CMD_DM select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI config TARGET_KZM9G bool "KZM9D board" @@ -119,6 +120,7 @@ config TARGET_STOUT imply CMD_DM select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI endchoice diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 1f26ada..6f4c513 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -13,3 +13,9 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o + +ifndef CONFIG_SPL_BUILD +ifdef CONFIG_R8A7790 +obj-$(CONFIG_ARMV7_PSCI) += psci.o pm-r8a7790.o +endif +endif diff --git a/arch/arm/mach-rmobile/pm-r8a7790.c b/arch/arm/mach-rmobile/pm-r8a7790.c new file mode 100644 index 000..c635cf6 --- /dev/null +++ b/arch/arm/mach-rmobile/pm-r8a7790.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CPU power management support for Renesas r8a7790 SoC + * + * Contains functions to control ARM Cortex A15/A7 cores and + * related peripherals basically used for PSCI. + * + * Copyright (C) 2018 EPAM Systems Inc. + * + * Mainly based on Renesas R-Car Gen2 platform code from Linux: + *arch/arm/mach-shmobile/... + */ + +#include +#include +#include + +#include "pm-r8a7790.h" + +/* + * APMU definitions + */ +#define CA15_APMU_BASE 0xe6152000 +#define CA7_APMU_BASE 0xe6151000 + +/* Wake Up Control Register */ +#define WUPCR_OFFS 0x10 +/* Power Status Register */ +#define PSTR_OFFS 0x40 +/* CPUn Power Status Control Register */ +#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) + +#define CPUPWR_STANDBY 0x3 + +/* Debug Resource Reset Control Register */ +#define DBGRCR_OFFS0x180 + +#define DBGCPUREN BIT(24) /* CPU Other Reset Req Enable */ +#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Req Enable */ +#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req Enable */ + +/* + * RST definitions + */ +#define RST_BASE 0xe616 + +/* Boot Address Registers */ +#define CA15BAR0x20 +#define CA7BAR 0x30 + +/* Reset Control Registers */ +#define CA15RESCNT 0x40 +#define CA7RESCNT 0x44 + +#define CA15RESCNT_CODE0xa5a5 +#define CA7RESCNT_CODE 0x5a5a + +/* SYS Boot Address Register */ +#define SBAR_BAREN BIT(4) /* SBAR is valid */ + +/* Watchdog Timer Reset Control Register */ +#define WDTRSTCR 0x54 + +#define WDTRSTCR_CODE 0xa55a + +/* + * SYSC definitions + */ +#define SYSC_BASE 0xe618 + +/* SYSC Status Register */ +#define SYSCSR 0x00 +/* Interrupt Status Register */ +#define SYSCISR0x04 +/* Interrupt Status Clear Register */ +#define SYSCISCR 0x08 +/* Interrupt Enable Register */ +#define SYSCIER0x0c +/* Interrupt Mask Register */ +#define SYSCIMR0x10 + +/* Power Status Register */ +#define PWRSR_OFFS 0x00 +/* Power Resume Control Register */ +#define PWRONCR_OFFS 0x0c +/* Power Shutoff/Resume Error Register */ +#define PWRER_OFFS 0x14 + +/* PWRSR5 .. PWRER5 */ +#define CA15_SCU_CHAN_OFFS 0x180 +/* PWRSR3 .. PWRER3 */ +#define
