Re: [U-Boot] [PATCH 2/3] sunxi: add DM I2C support for H3/H5

2018-01-25 Thread Maxime Ripard 
On Wed, Jan 24, 2018 at 12:00:58PM +0100, Nuno Gonçalves wrote:
> On Wed, Jan 24, 2018 at 11:57 AM, Maxime Ripard
>  wrote:
> > Why don't you just synchronize the DT with Linux?
> 
> Didn't know that was the usual approach. But in Linux the files have a
> different structure, for example there is sunxi-h3-h5.dtsi.

Yes, but nothing prevents us to have the same one here.

Maxime

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Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [U-Boot] [PATCH 2/3] sunxi: add DM I2C support for H3/H5

2018-01-24 Thread Nuno Gonçalves 
On Wed, Jan 24, 2018 at 11:57 AM, Maxime Ripard
 wrote:
> Why don't you just synchronize the DT with Linux?

Didn't know that was the usual approach. But in Linux the files have a
different structure, for example there is sunxi-h3-h5.dtsi.

Thanks,
Nuno
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[U-Boot] [PATCH 2/3] sunxi: add DM I2C support for H3/H5

2018-01-24 Thread Nuno Goncalves 
Signed-off-by: Nuno Goncalves 
---
 arch/arm/dts/sun8i-h3.dtsi | 48 ++
 arch/arm/include/asm/arch-sunxi/gpio.h |  2 ++
 board/sunxi/board.c| 10 ++-
 3 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index df2742095e..da17dfa579 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -396,6 +396,21 @@
drive-strength = <10>;
bias-disable;
};
+
+   i2c0_pins_a: i2c0@0 {
+   pins = "PA11", "PA12";
+   function = "i2c0";
+   };
+
+   i2c1_pins_a: i2c1@0 {
+   pins = "PA18", "PA19";
+   function = "i2c1";
+   };
+
+   i2c2_pins_a: i2c2@0 {
+   pins = "PE12", "PE13";
+   function = "i2c2";
+   };
};
 
timer@01c20c00 {
@@ -464,6 +479,39 @@
status = "disabled";
};
 
+   i2c0: i2c@01c2ac00 {
+   compatible = "allwinner,sun6i-a31-i2c";
+   reg = <0x01c2ac00 0x400>;
+   interrupts = ;
+   clocks = < CLK_BUS_I2C0>;
+   resets = < RST_BUS_I2C0>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   i2c1: i2c@01c2b000 {
+   compatible = "allwinner,sun6i-a31-i2c";
+   reg = <0x01c2b000 0x400>;
+   interrupts = ;
+   clocks = < CLK_BUS_I2C1>;
+   resets = < RST_BUS_I2C1>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   i2c2: i2c@01c2b400 {
+   compatible = "allwinner,sun6i-a31-i2c";
+   reg = <0x01c2b400 0x400>;
+   interrupts = ;
+   clocks = < CLK_BUS_I2C2>;
+   resets = < RST_BUS_I2C2>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
emac: ethernet@1c3 {
compatible = "allwinner,sun8i-h3-emac";
reg = <0x01c3 0x104>, <0x01c00030 0x4>;
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 24f85206c8..52884886d7 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -149,6 +149,8 @@ enum sunxi_gpio_number {
 #define SUN6I_GPA_SDC2 5
 #define SUN6I_GPA_SDC3 4
 #define SUN8I_H3_GPA_UART0 2
+#define SUN8I_H3_H5_GPA_TWI0   2
+#define SUN8I_H3_H5_GPA_TWI1   3
 
 #define SUN4I_GPB_PWM  2
 #define SUN4I_GPB_TWI0 2
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index dcacdf3e62..6b55aef202 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -93,6 +93,10 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUNXI_H3_H5)
+   sunxi_gpio_set_cfgpin(SUNXI_GPA(11), SUN8I_H3_H5_GPA_TWI0);
+   sunxi_gpio_set_cfgpin(SUNXI_GPA(12), SUN8I_H3_H5_GPA_TWI0);
+   clock_twi_onoff(0, 1);
 #elif defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
@@ -115,6 +119,10 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUNXI_H3_H5)
+   sunxi_gpio_set_cfgpin(SUNXI_GPA(18), SUN8I_H3_H5_GPA_TWI1);
+   sunxi_gpio_set_cfgpin(SUNXI_GPA(19), SUN8I_H3_H5_GPA_TWI1);
+   clock_twi_onoff(1, 1);
 #elif defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
@@ -137,7 +145,7 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN8I)
+#elif defined(CONFIG_MACH_SUN8I) /* same for CONFIG_MACH_SUNXI_H3_H5 */
sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
sunxi_gpio_set_cfgpin(SUNXI_GPE(13),

Re: [U-Boot] [PATCH 2/3] sunxi: add DM I2C support for H3/H5

2018-01-24 Thread Maxime Ripard 
Hi,

On Wed, Jan 24, 2018 at 11:01:52AM +0100, Nuno Goncalves wrote:
> Signed-off-by: Nuno Goncalves 

Please write a commit log.

> ---
>  arch/arm/dts/sun8i-h3.dtsi | 48 
> ++
>  arch/arm/include/asm/arch-sunxi/gpio.h |  2 ++
>  board/sunxi/board.c| 10 ++-
>  3 files changed, 59 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
> index df2742095e..da17dfa579 100644
> --- a/arch/arm/dts/sun8i-h3.dtsi
> +++ b/arch/arm/dts/sun8i-h3.dtsi
> @@ -396,6 +396,21 @@
>   drive-strength = <10>;
>   bias-disable;
>   };
> +
> + i2c0_pins_a: i2c0@0 {
> + pins = "PA11", "PA12";
> + function = "i2c0";
> + };
> +
> + i2c1_pins_a: i2c1@0 {
> + pins = "PA18", "PA19";
> + function = "i2c1";
> + };
> +
> + i2c2_pins_a: i2c2@0 {
> + pins = "PE12", "PE13";
> + function = "i2c2";
> + };
>   };
>  
>   timer@01c20c00 {
> @@ -464,6 +479,39 @@
>   status = "disabled";
>   };
>  
> + i2c0: i2c@01c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = ;
> + clocks = < CLK_BUS_I2C0>;
> + resets = < RST_BUS_I2C0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@01c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = ;
> + clocks = < CLK_BUS_I2C1>;
> + resets = < RST_BUS_I2C1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@01c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = ;
> + clocks = < CLK_BUS_I2C2>;
> + resets = < RST_BUS_I2C2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +

Why don't you just synchronize the DT with Linux?

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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