Re: [U-Boot] [PATCH 2/3] usb: zynqmp: Add XHCI driver support
On Tuesday, August 04, 2015 at 09:33:27 AM, Siva Durga Prasad Paladugu wrote:
Added USB XHCI driver support for zynqmp.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
[...]
Hi,
You'd have much more success if you actually CCed me with the patches.
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct zynqmp_xhci zynqmp_xhci;
+
+unsigned long ctr_addr[] = {ZYNQMP_USB0_XHCI_BASEADDR,
+ ZYNQMP_USB1_XHCI_BASEADDR};
Will you always init both controllers ?
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
Is such a lengthy delay really needed ?
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
[...]
+static int zynqmp_xhci_core_exit(struct zynqmp_xhci *zynqmp_xhci)
+{
+ /*
+ * Currently zynqmp socs do not support PHY shutdown from
+ * sw. But this support may be added in future socs.
+ */
+ return 0;
Please wrap this into xhci_hcd_stop(), no need for this ad-hoc function.
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor
**hcor) +{
+ struct zynqmp_xhci *ctx = zynqmp_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)ctr_addr[index];
+ ctx-dwc3_reg = (struct dwc3 *)((char *)(ctx-hcd) + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = zynqmp_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)ctx-hcd;
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(zynqmp-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct zynqmp_xhci *ctx = zynqmp_xhci;
+
+ zynqmp_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-zynqmp.h
b/include/linux/usb/xhci-zynqmp.h new file mode 100644
index 000..c384f91
--- /dev/null
+++ b/include/linux/usb/xhci-zynqmp.h
@@ -0,0 +1,56 @@
You should just wrap all of this header into the xhci-zynqmp.c and be
done with it, no need for ad-hoc file.
+/*
+ * Copyright 2015 Xilinx, Inc.
+ *
+ * Zynq USB HOST xHCI Controller
+ *
+ * Author: Siva Durga Prasad Paladugusiva...@xilinx.com
+ *
+ * This file was resused from Freescale USB xHCI
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_ZYNQMP_H_
+#define _ASM_ARCH_XHCI_ZYNQMP_H_
+
+/* Default to the FSL XHCI defines */
FSL XHCI ? Really now, I thought this was a xilinx chip.
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERON BIT(14)
+#define USB3_PHY_TX_POWERON BIT(15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON |
USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT 14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET BIT(17)
+#define USBOTGSS_DMADISABLE BIT(16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
+#define USBOTGSS_STANDBYMODE_SMRTBIT(5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 4)
+#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
+#define USBOTGSS_IDLEMODE_SMRT BIT(3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN BIT(1)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
+
+struct zynqmp_xhci {
+ struct xhci_hccr *hcd;
+ struct dwc3 *dwc3_reg;
This definitelly should not be in a header file.
+};
+
[U-Boot] [PATCH 2/3] usb: zynqmp: Add XHCI driver support
Added USB XHCI driver support for zynqmp.
Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com
---
drivers/usb/host/Makefile |1 +
drivers/usb/host/xhci-zynqmp.c | 113 +++
include/linux/usb/xhci-zynqmp.h | 56 +++
3 files changed, 170 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/xhci-zynqmp.c
create mode 100644 include/linux/usb/xhci-zynqmp.h
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6cc3bbd..73d6bcb 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c
new file mode 100644
index 000..d56bd17
--- /dev/null
+++ b/drivers/usb/host/xhci-zynqmp.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2015 Xilinx, Inc.
+ *
+ * Zynq USB HOST xHCI Controller
+ *
+ * Author: Siva Durga Prasad Paladugusiva...@xilinx.com
+ *
+ * This file was resused from Freescale USB xHCI
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+#include asm/arch-zynqmp/hardware.h
+#include linux/compat.h
+#include linux/usb/xhci-zynqmp.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct zynqmp_xhci zynqmp_xhci;
+
+unsigned long ctr_addr[] = {ZYNQMP_USB0_XHCI_BASEADDR,
+ ZYNQMP_USB1_XHCI_BASEADDR};
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(zynqmp_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(zynqmp_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int zynqmp_xhci_core_exit(struct zynqmp_xhci *zynqmp_xhci)
+{
+ /*
+* Currently zynqmp socs do not support PHY shutdown from
+* sw. But this support may be added in future socs.
+*/
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct zynqmp_xhci *ctx = zynqmp_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)ctr_addr[index];
+ ctx-dwc3_reg = (struct dwc3 *)((char *)(ctx-hcd) + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = zynqmp_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)ctx-hcd;
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(zynqmp-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct zynqmp_xhci *ctx = zynqmp_xhci;
+
+ zynqmp_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-zynqmp.h b/include/linux/usb/xhci-zynqmp.h
new file mode 100644
index 000..c384f91
--- /dev/null
+++ b/include/linux/usb/xhci-zynqmp.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2015 Xilinx, Inc.
+ *
+ * Zynq USB HOST xHCI Controller
+ *
+ * Author: Siva Durga Prasad Paladugusiva...@xilinx.com
+ *
+ * This file was resused from Freescale USB xHCI
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_ZYNQMP_H_
+#define _ASM_ARCH_XHCI_ZYNQMP_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERONBIT(14)
+#define USB3_PHY_TX_POWERON
