Re: [U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
Hi Daniel, The 03/15/2019 13:02, Daniel Schwierzeck wrote: > External E-Mail > > > Hi Horatio, > > Am 06.03.19 um 23:11 schrieb Horatiu Vultur: > > Hi Daniel, > > > > The 03/06/2019 14:19, Daniel Schwierzeck wrote: > >> > >> > >> Am 05.03.19 um 12:57 schrieb Horatiu Vultur: > >>> In Jaguar2 SoC family there are 3 different pcb. Each of this needs > >>> to configure the SerDes and the phys in different ways. > >>> Therefore implement the function board_phy_config and serdes_cfg > >>> and based on pcb configure them accordingly. > >> > >> what are the differences between all boards? Can't you model the > >> different register values somehow as custom DT properties? This method > >> looks like a lot of code duplication and doesn't scale well when adding > >> new boards. > > > > So there are following boards: > > - pcb110: it has viper phys that are connected to serdes1g using the > >interface sgmii > > - pcb111: it has atom phys that are connected to serdes6g using the > >interface qsgmii > > - pcb112: it has viper phys that are connected to serdes6g using the > >interface sgmii. > > > > Do you have an example where I can look, how to add this custom > > properties? > > > > Yes, it looks like a lot code duplication, but there are only few > > differences between them. I was thinking maybe I can create 2 functions > > that configure the serdes1g and serdes6g which will get as a paramenter > > the interface mode. In this way I think it would scale better, because > > then each new board it would just call these new functions. > > > > /Horatiu > > but this code belongs to the ethernet driver. Board specific differences > like PHY interface or Serdes type could be configured via appropiate > device-tree bindings (PHY interface already exists as generic binding). > How do you plan to do it in Linux? I understand now. Currently there is no Jaguar2 support on the upstream kernel, maybe at a later point in time will come this. > > I've found Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt > which looks very similar to what you want to achieve here. Maybe the > Bootlin guys can give you some more hints ;) I managed to talk with Alexandre and he proposed to have a look over the comphy inside the u-boot. Therefore I will have a look over this and I will send a new patch series. Thank you. > > > > > >> > >>> > >>> Signed-off-by: Horatiu Vultur > >>> --- > >>> board/mscc/jr2/jr2.c | 542 > >>> +++ > >>> 1 file changed, 542 insertions(+) > >>> > >>> diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c > >>> index 58a4a04..94e0c5d 100644 > >>> --- a/board/mscc/jr2/jr2.c > >>> +++ b/board/mscc/jr2/jr2.c > >>> @@ -6,6 +6,140 @@ > >>> #include > >>> #include > >>> #include > >>> +#include > >>> + > >>> +#define HSIO_ANA_SERDES1G_DES_CFG0xac > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << > >>> 1) > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << > >>> 5) > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << > >>> 8) > >>> +#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << > >>> 13) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << > >>> 6) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << > >>> 19) > >>> +#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << > >>> 24) > >>> +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 > >>> +#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) > >>> +#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << > >>> 4) > >>> +#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << > >>> 10) > >>> +#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << > >>> 13) > >>> +#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << > >>> 17) > >>> +#define HSIO_ANA_SERDES1G_SER_CFG0xb8 > >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc > >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) > >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) > >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) > >>> +#define HSIO_ANA_SERDES1G_PLL_CFG0xc0 > >>> +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) > >>> +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << > >>> 8) > >>> +#define
Re: [U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
Hi Horatio, Am 06.03.19 um 23:11 schrieb Horatiu Vultur: > Hi Daniel, > > The 03/06/2019 14:19, Daniel Schwierzeck wrote: >> >> >> Am 05.03.19 um 12:57 schrieb Horatiu Vultur: >>> In Jaguar2 SoC family there are 3 different pcb. Each of this needs >>> to configure the SerDes and the phys in different ways. >>> Therefore implement the function board_phy_config and serdes_cfg >>> and based on pcb configure them accordingly. >> >> what are the differences between all boards? Can't you model the >> different register values somehow as custom DT properties? This method >> looks like a lot of code duplication and doesn't scale well when adding >> new boards. > > So there are following boards: > - pcb110: it has viper phys that are connected to serdes1g using the >interface sgmii > - pcb111: it has atom phys that are connected to serdes6g using the >interface qsgmii > - pcb112: it has viper phys that are connected to serdes6g using the >interface sgmii. > > Do you have an example where I can look, how to add this custom > properties? > > Yes, it looks like a lot code duplication, but there are only few > differences between them. I was thinking maybe I can create 2 functions > that configure the serdes1g and serdes6g which will get as a paramenter > the interface mode. In this way I think it would scale better, because > then each new board it would just call these new functions. > > /Horatiu but this code belongs to the ethernet driver. Board specific differences like PHY interface or Serdes type could be configured via appropiate device-tree bindings (PHY interface already exists as generic binding). How do you plan to do it in Linux? I've found Documentation/devicetree/bindings/phy/phy-ocelot-serdes.txt which looks very similar to what you want to achieve here. Maybe the Bootlin guys can give you some more hints ;) > >> >>> >>> Signed-off-by: Horatiu Vultur >>> --- >>> board/mscc/jr2/jr2.c | 542 >>> +++ >>> 1 file changed, 542 insertions(+) >>> >>> diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c >>> index 58a4a04..94e0c5d 100644 >>> --- a/board/mscc/jr2/jr2.c >>> +++ b/board/mscc/jr2/jr2.c >>> @@ -6,6 +6,140 @@ >>> #include >>> #include >>> #include >>> +#include >>> + >>> +#define HSIO_ANA_SERDES1G_DES_CFG 0xac >>> +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << >>> 1) >>> +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << >>> 5) >>> +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << >>> 8) >>> +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << >>> 13) >>> +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 >>> +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) >>> +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << >>> 6) >>> +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) >>> +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) >>> +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) >>> +#defineHSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << >>> 19) >>> +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << >>> 24) >>> +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 >>> +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) >>> +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << >>> 4) >>> +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << >>> 10) >>> +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << >>> 13) >>> +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << >>> 17) >>> +#define HSIO_ANA_SERDES1G_SER_CFG 0xb8 >>> +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc >>> +#defineHSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) >>> +#defineHSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) >>> +#defineHSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) >>> +#define HSIO_ANA_SERDES1G_PLL_CFG 0xc0 >>> +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) >>> +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << >>> 8) >>> +#defineHSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) >>> +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8 >>> +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4 >>> +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc >>> +#defineHSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) >>> +#define HSIO_MCB_SERDES1G_CFG 0xe8 >>> +#defineHSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) >>> +#defineHSIO_MCB_SERDES1G_CFG_ADDR(x) (x) >>> + >>> +#define HSIO_ANA_SERDES6G_DES_CFG 0x11c >>>
Re: [U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
Hi Daniel, The 03/06/2019 14:19, Daniel Schwierzeck wrote: > > > Am 05.03.19 um 12:57 schrieb Horatiu Vultur: > > In Jaguar2 SoC family there are 3 different pcb. Each of this needs > > to configure the SerDes and the phys in different ways. > > Therefore implement the function board_phy_config and serdes_cfg > > and based on pcb configure them accordingly. > > what are the differences between all boards? Can't you model the > different register values somehow as custom DT properties? This method > looks like a lot of code duplication and doesn't scale well when adding > new boards. So there are following boards: - pcb110: it has viper phys that are connected to serdes1g using the interface sgmii - pcb111: it has atom phys that are connected to serdes6g using the interface qsgmii - pcb112: it has viper phys that are connected to serdes6g using the interface sgmii. Do you have an example where I can look, how to add this custom properties? Yes, it looks like a lot code duplication, but there are only few differences between them. I was thinking maybe I can create 2 functions that configure the serdes1g and serdes6g which will get as a paramenter the interface mode. In this way I think it would scale better, because then each new board it would just call these new functions. /Horatiu > > > > > Signed-off-by: Horatiu Vultur > > --- > > board/mscc/jr2/jr2.c | 542 > > +++ > > 1 file changed, 542 insertions(+) > > > > diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c > > index 58a4a04..94e0c5d 100644 > > --- a/board/mscc/jr2/jr2.c > > +++ b/board/mscc/jr2/jr2.c > > @@ -6,6 +6,140 @@ > > #include > > #include > > #include > > +#include > > + > > +#define HSIO_ANA_SERDES1G_DES_CFG 0xac > > +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << > > 1) > > +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << > > 5) > > +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << > > 8) > > +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << > > 13) > > +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 > > +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << > > 6) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << > > 19) > > +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << > > 24) > > +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 > > +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << > > 4) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << > > 10) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << > > 13) > > +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << > > 17) > > +#define HSIO_ANA_SERDES1G_SER_CFG 0xb8 > > +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc > > +#defineHSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) > > +#defineHSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) > > +#defineHSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) > > +#define HSIO_ANA_SERDES1G_PLL_CFG 0xc0 > > +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) > > +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << > > 8) > > +#defineHSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) > > +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8 > > +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4 > > +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc > > +#defineHSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) > > +#define HSIO_MCB_SERDES1G_CFG 0xe8 > > +#defineHSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) > > +#defineHSIO_MCB_SERDES1G_CFG_ADDR(x) (x) > > + > > +#define HSIO_ANA_SERDES6G_DES_CFG 0x11c > > +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_ANA BIT(0) > > +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_ANA(x) ((x) << > > 1) > > +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_HYST BIT(4) > > +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_HYST(x)((x) << > > 5) > > +#defineHSIO_ANA_SERDES6G_DES_CFG_CPMD_SEL(x) ((x) << > > 8) > > +#defineHSIO_ANA_SERDES6G_DES_CFG_MBTR_CTRL(x) ((x) << > > 10) > > +#define
Re: [U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
Am 05.03.19 um 12:57 schrieb Horatiu Vultur: > In Jaguar2 SoC family there are 3 different pcb. Each of this needs > to configure the SerDes and the phys in different ways. > Therefore implement the function board_phy_config and serdes_cfg > and based on pcb configure them accordingly. what are the differences between all boards? Can't you model the different register values somehow as custom DT properties? This method looks like a lot of code duplication and doesn't scale well when adding new boards. > > Signed-off-by: Horatiu Vultur > --- > board/mscc/jr2/jr2.c | 542 > +++ > 1 file changed, 542 insertions(+) > > diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c > index 58a4a04..94e0c5d 100644 > --- a/board/mscc/jr2/jr2.c > +++ b/board/mscc/jr2/jr2.c > @@ -6,6 +6,140 @@ > #include > #include > #include > +#include > + > +#define HSIO_ANA_SERDES1G_DES_CFG0xac > +#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << > 1) > +#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << > 5) > +#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << > 8) > +#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << > 13) > +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 > +#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) > +#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << > 6) > +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) > +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) > +#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) > +#define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << > 19) > +#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << > 24) > +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 > +#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) > +#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << > 4) > +#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << > 10) > +#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << > 13) > +#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << > 17) > +#define HSIO_ANA_SERDES1G_SER_CFG0xb8 > +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc > +#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) > +#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) > +#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) > +#define HSIO_ANA_SERDES1G_PLL_CFG0xc0 > +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) > +#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << > 8) > +#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) > +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8 > +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4 > +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc > +#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) > +#define HSIO_MCB_SERDES1G_CFG0xe8 > +#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) > +#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x) > + > +#define HSIO_ANA_SERDES6G_DES_CFG0x11c > +#define HSIO_ANA_SERDES6G_DES_CFG_SWAP_ANA BIT(0) > +#define HSIO_ANA_SERDES6G_DES_CFG_BW_ANA(x) ((x) << > 1) > +#define HSIO_ANA_SERDES6G_DES_CFG_SWAP_HYST BIT(4) > +#define HSIO_ANA_SERDES6G_DES_CFG_BW_HYST(x)((x) << > 5) > +#define HSIO_ANA_SERDES6G_DES_CFG_CPMD_SEL(x) ((x) << > 8) > +#define HSIO_ANA_SERDES6G_DES_CFG_MBTR_CTRL(x) ((x) << > 10) > +#define HSIO_ANA_SERDES6G_DES_CFG_PHS_CTRL(x) ((x) << > 13) > +#define HSIO_ANA_SERDES6G_IB_CFG 0x120 > +#define HSIO_ANA_SERDES6G_IB_CFG_REG_ENABIT(0) > +#define HSIO_ANA_SERDES6G_IB_CFG_EQZ_ENABIT(1) > +#define HSIO_ANA_SERDES6G_IB_CFG_SAM_ENABIT(2) > +#define HSIO_ANA_SERDES6G_IB_CFG_CAL_ENABIT(3) > +#define HSIO_ANA_SERDES6G_IB_CFG_CONCUR BIT(4) > +#define HSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENABIT(5) > +#define HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(x) ((x) << > 7) > +#define HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(x) ((x) << > 9) > +#define HSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(x) ((x) << > 11) > +#define
[U-Boot] [PATCH 2/4] board: mscc: jr2: Update MSCC Jaguar2 boards
In Jaguar2 SoC family there are 3 different pcb. Each of this needs to configure the SerDes and the phys in different ways. Therefore implement the function board_phy_config and serdes_cfg and based on pcb configure them accordingly. Signed-off-by: Horatiu Vultur --- board/mscc/jr2/jr2.c | 542 +++ 1 file changed, 542 insertions(+) diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 58a4a04..94e0c5d 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -6,6 +6,140 @@ #include #include #include +#include + +#define HSIO_ANA_SERDES1G_DES_CFG 0xac +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)((x) << 1) +#defineHSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) +#defineHSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES1G_IB_CFG 0xb0 +#defineHSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMPBIT(9) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) +#defineHSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) +#defineHSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19) +#defineHSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) +#define HSIO_ANA_SERDES1G_OB_CFG 0xb4 +#defineHSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) +#defineHSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)((x) << 4) +#defineHSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)((x) << 13) +#defineHSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) +#define HSIO_ANA_SERDES1G_SER_CFG 0xb8 +#define HSIO_ANA_SERDES1G_COMMON_CFG 0xbc +#defineHSIO_ANA_SERDES1G_COMMON_CFG_IF_MODEBIT(0) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) +#defineHSIO_ANA_SERDES1G_COMMON_CFG_SYS_RSTBIT(31) +#define HSIO_ANA_SERDES1G_PLL_CFG 0xc0 +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) +#defineHSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8) +#defineHSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) +#define HSIO_DIG_SERDES1G_DFT_CFG0 0xc8 +#define HSIO_DIG_SERDES1G_TP_CFG 0xd4 +#define HSIO_DIG_SERDES1G_MISC_CFG 0xdc +#defineHSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) +#define HSIO_MCB_SERDES1G_CFG 0xe8 +#defineHSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) +#defineHSIO_MCB_SERDES1G_CFG_ADDR(x) (x) + +#define HSIO_ANA_SERDES6G_DES_CFG 0x11c +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_ANA BIT(0) +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_ANA(x) ((x) << 1) +#defineHSIO_ANA_SERDES6G_DES_CFG_SWAP_HYST BIT(4) +#defineHSIO_ANA_SERDES6G_DES_CFG_BW_HYST(x)((x) << 5) +#defineHSIO_ANA_SERDES6G_DES_CFG_CPMD_SEL(x) ((x) << 8) +#defineHSIO_ANA_SERDES6G_DES_CFG_MBTR_CTRL(x) ((x) << 10) +#defineHSIO_ANA_SERDES6G_DES_CFG_PHS_CTRL(x) ((x) << 13) +#define HSIO_ANA_SERDES6G_IB_CFG 0x120 +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_ENABIT(0) +#defineHSIO_ANA_SERDES6G_IB_CFG_EQZ_ENABIT(1) +#defineHSIO_ANA_SERDES6G_IB_CFG_SAM_ENABIT(2) +#defineHSIO_ANA_SERDES6G_IB_CFG_CAL_ENABIT(3) +#defineHSIO_ANA_SERDES6G_IB_CFG_CONCUR BIT(4) +#defineHSIO_ANA_SERDES6G_IB_CFG_SIG_DET_ENABIT(5) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_OFF(x) ((x) << 7) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_LP(x) ((x) << 9) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_MID(x) ((x) << 11) +#defineHSIO_ANA_SERDES6G_IB_CFG_REG_PAT_SEL_HP(x) ((x) << 13) +#defineHSIO_ANA_SERDES6G_IB_CFG_SIG_DET_CLK_SEL(x) ((x) << 15) +#defineHSIO_ANA_SERDES6G_IB_CFG_TERM_MODE_SEL(x) ((x) << 18) +#defineHSIO_ANA_SERDES6G_IB_CFG_ICML_ADJ(x)((x) << 20) +#defineHSIO_ANA_SERDES6G_IB_CFG_RTRM_ADJ(x)((x) <<
