From: haikun haikun.w...@freescale.com
Bring in required device tree files for ls1021a from Linux.
These are initially unchanged and have a number of pieces not needed by U-Boot.
Signed-off-by: Haikun Wang haikun.w...@freescale.com
---
arch/arm/dts/Makefile| 3 +
arch/arm/dts/ls1021a-qds.dts | 201 +++
arch/arm/dts/ls1021a-twr.dts | 88 ++
arch/arm/dts/ls1021a.dtsi| 370 +++
4 files changed, 662 insertions(+)
create mode 100644 arch/arm/dts/ls1021a-qds.dts
create mode 100644 arch/arm/dts/ls1021a-twr.dts
create mode 100644 arch/arm/dts/ls1021a.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cbe5b86..67b821a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) += \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_TARGET_LS1021AQDS) += ls1021a-qds.dtb
+dtb-$(CONFIG_TARGET_LS1021ATWR) += ls1021a-twr.dtb
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
new file mode 100644
index 000..c89f85e
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -0,0 +1,201 @@
+/*
+ * Freescale ls1021a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include ls1021a.dtsi
+
+/ {
+ model = LS1021A QDS Board;
+
+ aliases {
+ enet0_rgmii_phy = rgmii_phy1;
+ enet1_rgmii_phy = rgmii_phy2;
+ enet2_rgmii_phy = rgmii_phy3;
+ enet0_sgmii_phy = sgmii_phy1c;
+ enet1_sgmii_phy = sgmii_phy1d;
+ };
+};
+
+dspi0 {
+ bus-num = 0;
+ status = okay;
+
+ dspiflash: at45db021d@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = atmel,at45db021d, atmel,at45,
atmel,dataflash;
+ spi-max-frequency = 1600;
+ spi-cpol;
+ spi-cpha;
+ reg = 0;
+ };
+};
+
+i2c0 {
+ status = okay;
+
+ pca9547: mux@77 {
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ i2c@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x0;
+
+ ds3232: rtc@68 {
+ compatible = dallas,ds3232;
+ reg = 0x68;
+ interrupts = GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x2;
+
+ ina220@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+
+ ina220@41 {
+ compatible = ti,ina220;
+ reg = 0x41;
+ shunt-resistor = 1000;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x3;
+
+ eeprom@56 {
+ compatible = atmel,24c512;
+ reg = 0x56;
+ };
+
+ eeprom@57 {
+ compatible = atmel,24c512;
+ reg = 0x57;
+ };
+
+ adt7461a@4c {
+ compatible = adi,adt7461a;
+ reg = 0x4c;
+ };
+ };
+ };
+};
+
+ifc {
+ #address-cells = 2;
+ #size-cells = 1;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = 0x0 0x0 0x0 0x6000 0x0800
+ 0x2 0x0 0x0 0x7e80 0x0001
+ 0x3 0x0 0x0 0x7fb0 0x0100;
+ status = okay;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x800;
+ bank-width = 2;
+ device-width = 1;
+ };
+
+ fpga: board-control@3,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = simple-bus;
+ reg = 0x3 0x0 0x100;
+ bank-width = 1;
+ device-width = 1;
+ ranges = 0 3 0 0x100;
+
+ mdio-mux-emi1 {
+ compatible = mdio-mux-mmioreg;
+
