Re: [U-Boot] [PATCH 2/7] Tegra114: Add AVP (arm720t) files

2013-01-17 Thread Tom Warren 
Stephen,

On Wed, Jan 16, 2013 at 3:42 PM, Stephen Warren swar...@wwwdotorg.org wrote:
 On 01/16/2013 02:14 PM, Tom Warren wrote:
 This provides SPL support for T114 boards - AVP early init, plus
 CPU (A15) init/jump to main U-Boot.

 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.c

 - if (chip_id == 0x30)
 + if (chip_id = 0x30)
   return TEGRA_FAMILY_T3x;
   else
   return TEGRA_FAMILY_T2x;

 Shouldn't that comparison use CHIPID_TEGRA30?

 Shouldn't there be a TEGRA_FAMILY_T11x for Tegra114; anything that cares
 about =Tegra30 can compare the family with = not ==.

 Hmm. It seems the only use of the FAMILY value is get_num_cpus() right
 below; why not have that just switch on the same chip_id variable that
 everything else uses?

Sure, I can refine this code.  I didn't want to spend too much time
obsessively polishing my 'precious' and miss the upstreaming dates I'd
committed to.

But it's worth a look for V2.


 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.h

 +#ifndef TRUE
 +#define TRUE 1
 +#endif
 +#ifndef FALSE
 +#define FALSE0
 +#endif

 Surely those are in a standard header somewhere; we shouldn't create yet
 another duplicate of them.

Couldn't find 'em on a quick search (grep define.TRUE) except in
places like scsi.h and ext4_common.h and fpga.h. If you have a
standard header that you know of, let me know.


 diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c 
 b/arch/arm/cpu/arm720t/tegra114/cpu.c

 +static int is_partition_powered(u32 mask)

 + reg = readl(pmc-pmc_pwrgate_status);
 + if ((reg  mask) == mask)
 + return TRUE;
 +
 + return FALSE;

 The last 4 lines are just return reg  mask; or return (reg  mask)
 == mask;. Same in the next function.

I'm porting internal bootloader bringup code here, and trying to avoid
unnecessary changes, but I can modify these to remove the TRUE/FALSE
in V2.


 +void powerup_cpus(void)
 +{
 + debug(powerup_cpus entry\n);
 +
 + /* Are we booting to the fast cluster? */
 + if (get_cluster_id() == 0) {

 Why would we ever boot on anything other than the fast cluster? I would
 assume that the kernel assume it will always get booted on the fast
 cluster, which would then imply that U-Boot had to boot on or switch to
 the fast cluster.


Again, this is from internal NV bootloader code that I know works. I
don't know the circumstances where we might be booted on the LP
cluster, but I figured if the internal bootloader code thought it
worth checking, so should I.  If you have unimpeachable evidence to
the contrary, I can optimize this out.

Tom
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Re: [U-Boot] [PATCH 2/7] Tegra114: Add AVP (arm720t) files

2013-01-17 Thread Tom Warren 
Allen,

On Wed, Jan 16, 2013 at 4:01 PM, Allen Martin amar...@nvidia.com wrote:
 On Wed, Jan 16, 2013 at 01:14:03PM -0800, Tom Warren wrote:
 This provides SPL support for T114 boards - AVP early init, plus
 CPU (A15) init/jump to main U-Boot.

 Signed-off-by: Tom Warren twar...@nvidia.com
 ---
  arch/arm/cpu/arm720t/tegra-common/cpu.c |   23 ++-
  arch/arm/cpu/arm720t/tegra-common/cpu.h |   13 +-
  arch/arm/cpu/arm720t/tegra114/Makefile  |   42 
  arch/arm/cpu/arm720t/tegra114/config.mk |   19 ++
  arch/arm/cpu/arm720t/tegra114/cpu.c |  328 
 +++
  5 files changed, 411 insertions(+), 14 deletions(-)
  create mode 100644 arch/arm/cpu/arm720t/tegra114/Makefile
  create mode 100644 arch/arm/cpu/arm720t/tegra114/config.mk
  create mode 100644 arch/arm/cpu/arm720t/tegra114/cpu.c

 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.c
 index 693d584..846163c 100644
 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
 +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
 @@ -40,7 +40,7 @@ enum tegra_family_t get_family(void)
 chip_id = reg  8;
 chip_id = 0xff;
 debug(  tegra_get_family: chip_id = %x\n, chip_id);
 -   if (chip_id == 0x30)
 +   if (chip_id = 0x30)

 Should this be CHIPID_TEGRA30?  And it would probably be better to do:

 if (chipid == CHIPID_TEGRA30 || chipid == CHIPID_TEGRA114)
  return TEGRA_FAMILY_T3x;
 else if (chipid == CHIPID_TEGRA20)
  return TEGRA_FAMILY_T2x;
 else
  fail;


 That forces the person doing the support for the next tegra chip to
 have to make a conscious decision about what to do here.

Sounds good, will do in V2.



 return TEGRA_FAMILY_T3x;
 else
 return TEGRA_FAMILY_T2x;
 @@ -56,6 +56,7 @@ int get_num_cpus(void)
   */
  struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] 
 = {
 /* T20: 1 GHz */
 +   /*  n,  m, p, cpcon */
 {{ 1000, 13, 0, 12},/* OSC 13M */
  { 625,  12, 0, 8}, /* OSC 19.2M */
  { 1000, 12, 0, 12},/* OSC 12M */
 @@ -76,11 +77,11 @@ struct clk_pll_table 
 tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
  { 700, 13, 0, 8},
 },

 -   /* TEGRA_SOC2_SLOW: 312 MHz */
 -   {{ 312, 13, 0, 12}, /* OSC 13M */
 -{ 260, 16, 0, 8},  /* OSC 19.2M */
 -{ 312, 12, 0, 12}, /* OSC 12M */
 -{ 312, 26, 0, 12}, /* OSC 26M */

 Removing TEGRA_SOC2_SLOW should probably be a separate patch, since it
 doesn't hae anything to do with t114.

I did this in one of my patchset revisions for the T30 baseline code,
but it crept back in somehow when I got around to looking at T114
support.

I can make a separate patch and slip it in the /next on top of the
current commits, before I apply the T114 stuff if it's cleaner for
you.


 +   /* T114: 1.4 GHz */
 +   {{ 862, 8, 0, 8},
 +{ 583, 8, 0, 4},
 +{ 696, 12, 0, 8},
 +{ 700, 13, 0, 8},
 },
  };

 @@ -166,8 +167,8 @@ void init_pllx(void)
 sel = tegra_pll_x_table[chip_type][osc];
 pllx_set_rate(pll, sel-n, sel-m, sel-p, sel-cpcon);

 -   /* adjust PLLP_out1-4 on T30 */
 -   if (chip_type == TEGRA_SOC_T30) {
 +   /* adjust PLLP_out1-4 on T30/T114 */
 +   if (chip_type = TEGRA_SOC_T30) {

 same comment here about = T30

Will do.


 debug(  init_pllx: adjusting PLLP out freqs\n);
 adjust_pllp_out_freqs();
 }
 @@ -203,7 +204,7 @@ void enable_cpu_clock(int enable)
  */
 clk = readl(clkrst-crc_clk_cpu_cmplx);
 clk |= 1  CPU1_CLK_STP_SHIFT;
 -#if defined(CONFIG_TEGRA30)
 +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)

 Can this be runtime instead of #ifdef?

Not sure what you mean by runtime - this is common code. Are you
asking to make it based on a num_cpus variable, etc.?

if (num_cpus  2)
clk |= (1  CPU2_CLK_STP_SHIFT) + (1  CPU3_CLK_STP_SHIFT);



 clk |= 1  CPU2_CLK_STP_SHIFT;
 clk |= 1  CPU3_CLK_STP_SHIFT;
  #endif
 @@ -308,7 +309,7 @@ void clock_enable_coresight(int enable)
  * Clock divider request for 204MHz would setup CSITE clock 
 as
  * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 
 408MHz
  */
 -   if (tegra_get_chip_type() == TEGRA_SOC_T30)
 +   if (tegra_get_chip_type() = TEGRA_SOC_T30)

 same comment here about = T30

Will do.


 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
 else
 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
 @@ -318,7 +319,7 @@ void clock_enable_coresight(int enable)
 rst = CORESIGHT_UNLOCK;
 writel(rst, CSITE_CPU_DBG0_LAR);
 writel(rst, CSITE_CPU_DBG1_LAR);
 -#if defined(CONFIG_TEGRA30)
 +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)

 same comment here

Re: [U-Boot] [PATCH 2/7] Tegra114: Add AVP (arm720t) files

2013-01-17 Thread Stephen Warren 
On 01/17/2013 12:15 PM, Tom Warren wrote:
 Stephen,
 
 On Wed, Jan 16, 2013 at 3:42 PM, Stephen Warren swar...@wwwdotorg.org wrote:
 On 01/16/2013 02:14 PM, Tom Warren wrote:
 This provides SPL support for T114 boards - AVP early init, plus
 CPU (A15) init/jump to main U-Boot.

 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.h

 +#ifndef TRUE
 +#define TRUE 1
 +#endif
 +#ifndef FALSE
 +#define FALSE0
 +#endif

 Surely those are in a standard header somewhere; we shouldn't create yet
 another duplicate of them.
 
 Couldn't find 'em on a quick search (grep define.TRUE) except in
 places like scsi.h and ext4_common.h and fpga.h. If you have a
 standard header that you know of, let me know.

Hmmm. Further investigation shows it is indeed once of those standard
things that isn't actually defined anywhere standard:-(

 diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c 
 b/arch/arm/cpu/arm720t/tegra114/cpu.c

 +static int is_partition_powered(u32 mask)

 + reg = readl(pmc-pmc_pwrgate_status);
 + if ((reg  mask) == mask)
 + return TRUE;
 +
 + return FALSE;

 The last 4 lines are just return reg  mask; or return (reg  mask)
 == mask;. Same in the next function.
 
 I'm porting internal bootloader bringup code here, and trying to avoid
 unnecessary changes, but I can modify these to remove the TRUE/FALSE
 in V2.

I don't think our downstream code is relevant for upstreaming; changes
sent upstream should be clean/minimal/standalone. In fact, I find
upstreaming a good time to explicitly remove/clean-up all the cruft that
has accumulated downstream, which wasn't always thought through thoroughly.

 +void powerup_cpus(void)
 +{
 + debug(powerup_cpus entry\n);
 +
 + /* Are we booting to the fast cluster? */
 + if (get_cluster_id() == 0) {

 Why would we ever boot on anything other than the fast cluster? I would
 assume that the kernel assume it will always get booted on the fast
 cluster, which would then imply that U-Boot had to boot on or switch to
 the fast cluster.
 
 Again, this is from internal NV bootloader code that I know works. I
 don't know the circumstances where we might be booted on the LP
 cluster, but I figured if the internal bootloader code thought it
 worth checking, so should I.  If you have unimpeachable evidence to
 the contrary, I can optimize this out.

I think it's more that if we don't have concrete evidence that the code
is needed, we shouldn't bloat usptream with cruft.

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[U-Boot] [PATCH 2/7] Tegra114: Add AVP (arm720t) files

2013-01-16 Thread Tom Warren 
This provides SPL support for T114 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.

Signed-off-by: Tom Warren twar...@nvidia.com
---
 arch/arm/cpu/arm720t/tegra-common/cpu.c |   23 ++-
 arch/arm/cpu/arm720t/tegra-common/cpu.h |   13 +-
 arch/arm/cpu/arm720t/tegra114/Makefile  |   42 
 arch/arm/cpu/arm720t/tegra114/config.mk |   19 ++
 arch/arm/cpu/arm720t/tegra114/cpu.c |  328 +++
 5 files changed, 411 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/cpu/arm720t/tegra114/Makefile
 create mode 100644 arch/arm/cpu/arm720t/tegra114/config.mk
 create mode 100644 arch/arm/cpu/arm720t/tegra114/cpu.c

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c 
b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 693d584..846163c 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -40,7 +40,7 @@ enum tegra_family_t get_family(void)
chip_id = reg  8;
chip_id = 0xff;
debug(  tegra_get_family: chip_id = %x\n, chip_id);
-   if (chip_id == 0x30)
+   if (chip_id = 0x30)
return TEGRA_FAMILY_T3x;
else
return TEGRA_FAMILY_T2x;
@@ -56,6 +56,7 @@ int get_num_cpus(void)
  */
 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
/* T20: 1 GHz */
+   /*  n,  m, p, cpcon */
{{ 1000, 13, 0, 12},/* OSC 13M */
 { 625,  12, 0, 8}, /* OSC 19.2M */
 { 1000, 12, 0, 12},/* OSC 12M */
@@ -76,11 +77,11 @@ struct clk_pll_table 
tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
 { 700, 13, 0, 8},
},
 
-   /* TEGRA_SOC2_SLOW: 312 MHz */
-   {{ 312, 13, 0, 12}, /* OSC 13M */
-{ 260, 16, 0, 8},  /* OSC 19.2M */
-{ 312, 12, 0, 12}, /* OSC 12M */
-{ 312, 26, 0, 12}, /* OSC 26M */
+   /* T114: 1.4 GHz */
+   {{ 862, 8, 0, 8},
+{ 583, 8, 0, 4},
+{ 696, 12, 0, 8},
+{ 700, 13, 0, 8},
},
 };
 
@@ -166,8 +167,8 @@ void init_pllx(void)
sel = tegra_pll_x_table[chip_type][osc];
pllx_set_rate(pll, sel-n, sel-m, sel-p, sel-cpcon);
 
-   /* adjust PLLP_out1-4 on T30 */
-   if (chip_type == TEGRA_SOC_T30) {
+   /* adjust PLLP_out1-4 on T30/T114 */
+   if (chip_type = TEGRA_SOC_T30) {
debug(  init_pllx: adjusting PLLP out freqs\n);
adjust_pllp_out_freqs();
}
@@ -203,7 +204,7 @@ void enable_cpu_clock(int enable)
 */
clk = readl(clkrst-crc_clk_cpu_cmplx);
clk |= 1  CPU1_CLK_STP_SHIFT;
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
clk |= 1  CPU2_CLK_STP_SHIFT;
clk |= 1  CPU3_CLK_STP_SHIFT;
 #endif
@@ -308,7 +309,7 @@ void clock_enable_coresight(int enable)
 * Clock divider request for 204MHz would setup CSITE clock as
 * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
 */
-   if (tegra_get_chip_type() == TEGRA_SOC_T30)
+   if (tegra_get_chip_type() = TEGRA_SOC_T30)
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
else
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
@@ -318,7 +319,7 @@ void clock_enable_coresight(int enable)
rst = CORESIGHT_UNLOCK;
writel(rst, CSITE_CPU_DBG0_LAR);
writel(rst, CSITE_CPU_DBG1_LAR);
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
writel(rst, CSITE_CPU_DBG2_LAR);
writel(rst, CSITE_CPU_DBG3_LAR);
 #endif
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h 
b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index 3e2ea3a..45b346d 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -22,14 +22,21 @@
  */
 #include asm/types.h
 
+#ifndef TRUE
+#define TRUE   1
+#endif
+#ifndef FALSE
+#define FALSE  0
+#endif
+
 /* Stabilization delays, in usec */
 #define PLL_STABILIZATION_DELAY (300)
 #define IO_STABILIZATION_DELAY (1000)
 
-#if defined(CONFIG_TEGRA30)
-#define NVBL_PLLP_KHZ  (408000)
-#else  /* Tegra20 */
+#if defined(CONFIG_TEGRA20)
 #define NVBL_PLLP_KHZ  (216000)
+#else  /* Tegra30/Tegra114 */
+#define NVBL_PLLP_KHZ  (408000)
 #endif
 
 #define PLLX_ENABLED   (1  30)
diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile 
b/arch/arm/cpu/arm720t/tegra114/Makefile
new file mode 100644
index 000..157d85a
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra114/Makefile
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software

Re: [U-Boot] [PATCH 2/7] Tegra114: Add AVP (arm720t) files

2013-01-16 Thread Stephen Warren 
On 01/16/2013 02:14 PM, Tom Warren wrote:
 This provides SPL support for T114 boards - AVP early init, plus
 CPU (A15) init/jump to main U-Boot.

 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.c

 - if (chip_id == 0x30)
 + if (chip_id = 0x30)
   return TEGRA_FAMILY_T3x;
   else
   return TEGRA_FAMILY_T2x;

Shouldn't that comparison use CHIPID_TEGRA30?

Shouldn't there be a TEGRA_FAMILY_T11x for Tegra114; anything that cares
about =Tegra30 can compare the family with = not ==.

Hmm. It seems the only use of the FAMILY value is get_num_cpus() right
below; why not have that just switch on the same chip_id variable that
everything else uses?

 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.h

 +#ifndef TRUE
 +#define TRUE 1
 +#endif
 +#ifndef FALSE
 +#define FALSE0
 +#endif

Surely those are in a standard header somewhere; we shouldn't create yet
another duplicate of them.

 diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c 
 b/arch/arm/cpu/arm720t/tegra114/cpu.c

 +static int is_partition_powered(u32 mask)

 + reg = readl(pmc-pmc_pwrgate_status);
 + if ((reg  mask) == mask)
 + return TRUE;
 +
 + return FALSE;

The last 4 lines are just return reg  mask; or return (reg  mask)
== mask;. Same in the next function.

 +void powerup_cpus(void)
 +{
 + debug(powerup_cpus entry\n);
 +
 + /* Are we booting to the fast cluster? */
 + if (get_cluster_id() == 0) {

Why would we ever boot on anything other than the fast cluster? I would
assume that the kernel assume it will always get booted on the fast
cluster, which would then imply that U-Boot had to boot on or switch to
the fast cluster.

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Re: [U-Boot] [PATCH 2/7] Tegra114: Add AVP (arm720t) files

2013-01-16 Thread Allen Martin 
On Wed, Jan 16, 2013 at 01:14:03PM -0800, Tom Warren wrote:
 This provides SPL support for T114 boards - AVP early init, plus
 CPU (A15) init/jump to main U-Boot.
 
 Signed-off-by: Tom Warren twar...@nvidia.com
 ---
  arch/arm/cpu/arm720t/tegra-common/cpu.c |   23 ++-
  arch/arm/cpu/arm720t/tegra-common/cpu.h |   13 +-
  arch/arm/cpu/arm720t/tegra114/Makefile  |   42 
  arch/arm/cpu/arm720t/tegra114/config.mk |   19 ++
  arch/arm/cpu/arm720t/tegra114/cpu.c |  328 
 +++
  5 files changed, 411 insertions(+), 14 deletions(-)
  create mode 100644 arch/arm/cpu/arm720t/tegra114/Makefile
  create mode 100644 arch/arm/cpu/arm720t/tegra114/config.mk
  create mode 100644 arch/arm/cpu/arm720t/tegra114/cpu.c
 
 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.c
 index 693d584..846163c 100644
 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
 +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
 @@ -40,7 +40,7 @@ enum tegra_family_t get_family(void)
 chip_id = reg  8;
 chip_id = 0xff;
 debug(  tegra_get_family: chip_id = %x\n, chip_id);
 -   if (chip_id == 0x30)
 +   if (chip_id = 0x30)

Should this be CHIPID_TEGRA30?  And it would probably be better to do:

if (chipid == CHIPID_TEGRA30 || chipid == CHIPID_TEGRA114)
 return TEGRA_FAMILY_T3x;
else if (chipid == CHIPID_TEGRA20)
 return TEGRA_FAMILY_T2x;
else
 fail;


That forces the person doing the support for the next tegra chip to
have to make a conscious decision about what to do here.


 return TEGRA_FAMILY_T3x;
 else
 return TEGRA_FAMILY_T2x;
 @@ -56,6 +56,7 @@ int get_num_cpus(void)
   */
  struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] 
 = {
 /* T20: 1 GHz */
 +   /*  n,  m, p, cpcon */
 {{ 1000, 13, 0, 12},/* OSC 13M */
  { 625,  12, 0, 8}, /* OSC 19.2M */
  { 1000, 12, 0, 12},/* OSC 12M */
 @@ -76,11 +77,11 @@ struct clk_pll_table 
 tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
  { 700, 13, 0, 8},
 },
 
 -   /* TEGRA_SOC2_SLOW: 312 MHz */
 -   {{ 312, 13, 0, 12}, /* OSC 13M */
 -{ 260, 16, 0, 8},  /* OSC 19.2M */
 -{ 312, 12, 0, 12}, /* OSC 12M */
 -{ 312, 26, 0, 12}, /* OSC 26M */

Removing TEGRA_SOC2_SLOW should probably be a separate patch, since it
doesn't hae anything to do with t114.

 +   /* T114: 1.4 GHz */
 +   {{ 862, 8, 0, 8},
 +{ 583, 8, 0, 4},
 +{ 696, 12, 0, 8},
 +{ 700, 13, 0, 8},
 },
  };
 
 @@ -166,8 +167,8 @@ void init_pllx(void)
 sel = tegra_pll_x_table[chip_type][osc];
 pllx_set_rate(pll, sel-n, sel-m, sel-p, sel-cpcon);
 
 -   /* adjust PLLP_out1-4 on T30 */
 -   if (chip_type == TEGRA_SOC_T30) {
 +   /* adjust PLLP_out1-4 on T30/T114 */
 +   if (chip_type = TEGRA_SOC_T30) {

same comment here about = T30

 debug(  init_pllx: adjusting PLLP out freqs\n);
 adjust_pllp_out_freqs();
 }
 @@ -203,7 +204,7 @@ void enable_cpu_clock(int enable)
  */
 clk = readl(clkrst-crc_clk_cpu_cmplx);
 clk |= 1  CPU1_CLK_STP_SHIFT;
 -#if defined(CONFIG_TEGRA30)
 +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)

Can this be runtime instead of #ifdef?

 clk |= 1  CPU2_CLK_STP_SHIFT;
 clk |= 1  CPU3_CLK_STP_SHIFT;
  #endif
 @@ -308,7 +309,7 @@ void clock_enable_coresight(int enable)
  * Clock divider request for 204MHz would setup CSITE clock as
  * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
  */
 -   if (tegra_get_chip_type() == TEGRA_SOC_T30)
 +   if (tegra_get_chip_type() = TEGRA_SOC_T30)

same comment here about = T30

 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
 else
 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
 @@ -318,7 +319,7 @@ void clock_enable_coresight(int enable)
 rst = CORESIGHT_UNLOCK;
 writel(rst, CSITE_CPU_DBG0_LAR);
 writel(rst, CSITE_CPU_DBG1_LAR);
 -#if defined(CONFIG_TEGRA30)
 +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)

same comment here about runtime vs ifdef

 writel(rst, CSITE_CPU_DBG2_LAR);
 writel(rst, CSITE_CPU_DBG3_LAR);
  #endif
 diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h 
 b/arch/arm/cpu/arm720t/tegra-common/cpu.h
 index 3e2ea3a..45b346d 100644
 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
 +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
 @@ -22,14 +22,21 @@
   */
  #include asm/types.h
 
 +#ifndef TRUE
 +#define TRUE   1
 +#endif
 +#ifndef FALSE
 +#define FALSE  0
 +#endif
 +

u-boot seems a little inconsistent here, but it looks like most of
u-boot uses C99 true and false


  /* Stabilization delays, in usec */