Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Graeme, On Thu, Oct 25, 2012 at 9:15 PM, Graeme Russ graeme.r...@gmail.com wrote: Hi Simon, On Fri, Oct 26, 2012 at 1:36 PM, Simon Glass s...@chromium.org wrote: Hi Graeme, On Mon, Oct 22, 2012 at 11:33 PM, Graeme Russ graeme.r...@gmail.com wrote: Hi Simon, On Oct 23, 2012 4:42 PM, Simon Glass s...@chromium.org wrote: Hi Graeme, On Mon, Oct 22, 2012 at 10:38 PM, Graeme Russ graeme.r...@gmail.com wrote: Hi Simon, [snip] I plan on doing dev work on a AMD E350 based board 'soon'. The E350 is already supported by coreboot, so I'm planning on getting coreboot ported for this board and then run U-Boot from coreboot. So we can no longer assume all coreboot boards will be Intel based. Sounds good! Shall we rename coreboot.h to something like chromebook-x86.h? Even better would be to use the model name (which I assume would make the x86 tag redundant) Well, the model is very device-specific. So far as U-Boot cares all the models are basically the same. What differences there are are taken care of by device tree differences. This is try on ARM for machines which share the some SOC, and true for basically all x86 platforms. Key words: So far :) - If all the x86 chromebooks are essentially the same as far as U-Boot is concerned, then chromebook-x86.h will be fine. OK I assume the plan is to create a common U-Boot binary with drivers for all supported chromebook hardware and use the device tree (initially built by passing coreboot tables, but maybe one day in the future passed by coreboot) to determine which drivers to initialise? The device tree would then be further fleshed out by U-Boot and passed to the Linux kernel? Yes that's right, except that we don't currently pass an fdt to the kernel. I suspect we will start doing this at some point. Regards, Simon Regards, Graeme ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Graeme,
On Mon, Oct 22, 2012 at 11:33 PM, Graeme Russ graeme.r...@gmail.com wrote:
Hi Simon,
On Oct 23, 2012 4:42 PM, Simon Glass s...@chromium.org wrote:
Hi Graeme,
On Mon, Oct 22, 2012 at 10:38 PM, Graeme Russ graeme.r...@gmail.com
wrote:
Hi Simon,
On Tue, Oct 23, 2012 at 4:34 PM, Simon Glass s...@chromium.org wrote:
Hi Graeme,
On Thu, Oct 18, 2012 at 9:12 PM, Graeme Russ graeme.r...@gmail.com
wrote:
Hi Simon,
On Fri, Oct 19, 2012 at 2:45 PM, Simon Glass s...@chromium.org wrote:
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -45,6 +45,27 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE},
\
+ {PCI_VENDOR_ID_INTEL, \
+
PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
This implies every coreboot board is Intel. When you start to
introduce hardware specific U-Boot components, you need to introduce a
board specific config file.
Would it be better to have a CONFIG_X86_COREBOOT and a coreboot 'SoC'
and no coreboot board?
I am not sure about using the SOC - after all we might need that
concept soon on x86. Maybe we should create a new board config that
includes coreboot.h?
SoC was the wrong abstraction - I think coreboot library is better
(see my email I just sent)
Yes, ok. I can do a patch to move it, or do you want to?
I think it would be best for you to move it.
Presumably
this would come in after the patches that are already pending on the
mailing list?
Yes. No big hurry
Having said that I'm not sure how important it is right now. So far,
coreboot.h is actually a particular class of boards, all Intel based.
We can name it whatever we want when we actually have other boards
which are coreboot but not Intel. Up to you
I plan on doing dev work on a AMD E350 based board 'soon'. The E350 is
already supported by coreboot, so I'm planning on getting coreboot
ported for this board and then run U-Boot from coreboot. So we can no
longer assume all coreboot boards will be Intel based.
Sounds good! Shall we rename coreboot.h to something like
chromebook-x86.h?
Even better would be to use the model name (which I assume would make the
x86 tag redundant)
Well, the model is very device-specific. So far as U-Boot cares all
the models are basically the same. What differences there are are
taken care of by device tree differences. This is try on ARM for
machines which share the some SOC, and true for basically all x86
platforms.
Regards,
Simon
Regards,
Graeme
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Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Simon, On Fri, Oct 26, 2012 at 1:36 PM, Simon Glass s...@chromium.org wrote: Hi Graeme, On Mon, Oct 22, 2012 at 11:33 PM, Graeme Russ graeme.r...@gmail.com wrote: Hi Simon, On Oct 23, 2012 4:42 PM, Simon Glass s...@chromium.org wrote: Hi Graeme, On Mon, Oct 22, 2012 at 10:38 PM, Graeme Russ graeme.r...@gmail.com wrote: Hi Simon, [snip] I plan on doing dev work on a AMD E350 based board 'soon'. The E350 is already supported by coreboot, so I'm planning on getting coreboot ported for this board and then run U-Boot from coreboot. So we can no longer assume all coreboot boards will be Intel based. Sounds good! Shall we rename coreboot.h to something like chromebook-x86.h? Even better would be to use the model name (which I assume would make the x86 tag redundant) Well, the model is very device-specific. So far as U-Boot cares all the models are basically the same. What differences there are are taken care of by device tree differences. This is try on ARM for machines which share the some SOC, and true for basically all x86 platforms. Key words: So far :) - If all the x86 chromebooks are essentially the same as far as U-Boot is concerned, then chromebook-x86.h will be fine. I assume the plan is to create a common U-Boot binary with drivers for all supported chromebook hardware and use the device tree (initially built by passing coreboot tables, but maybe one day in the future passed by coreboot) to determine which drivers to initialise? The device tree would then be further fleshed out by U-Boot and passed to the Linux kernel? Regards, Graeme ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Simon,
On Oct 23, 2012 4:42 PM, Simon Glass s...@chromium.org wrote:
Hi Graeme,
On Mon, Oct 22, 2012 at 10:38 PM, Graeme Russ graeme.r...@gmail.com
wrote:
Hi Simon,
On Tue, Oct 23, 2012 at 4:34 PM, Simon Glass s...@chromium.org wrote:
Hi Graeme,
On Thu, Oct 18, 2012 at 9:12 PM, Graeme Russ graeme.r...@gmail.com
wrote:
Hi Simon,
On Fri, Oct 19, 2012 at 2:45 PM, Simon Glass s...@chromium.org wrote:
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -45,6 +45,27 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+
PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+
PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
This implies every coreboot board is Intel. When you start to
introduce hardware specific U-Boot components, you need to introduce a
board specific config file.
Would it be better to have a CONFIG_X86_COREBOOT and a coreboot 'SoC'
and no coreboot board?
I am not sure about using the SOC - after all we might need that
concept soon on x86. Maybe we should create a new board config that
includes coreboot.h?
SoC was the wrong abstraction - I think coreboot library is better
(see my email I just sent)
Yes, ok. I can do a patch to move it, or do you want to?
I think it would be best for you to move it.
Presumably
this would come in after the patches that are already pending on the
mailing list?
Yes. No big hurry
Having said that I'm not sure how important it is right now. So far,
coreboot.h is actually a particular class of boards, all Intel based.
We can name it whatever we want when we actually have other boards
which are coreboot but not Intel. Up to you
I plan on doing dev work on a AMD E350 based board 'soon'. The E350 is
already supported by coreboot, so I'm planning on getting coreboot
ported for this board and then run U-Boot from coreboot. So we can no
longer assume all coreboot boards will be Intel based.
Sounds good! Shall we rename coreboot.h to something like
chromebook-x86.h?
Even better would be to use the model name (which I assume would make the
x86 tag redundant)
Regards,
Graeme
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Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Graeme,
On Thu, Oct 18, 2012 at 9:12 PM, Graeme Russ graeme.r...@gmail.com wrote:
Hi Simon,
On Fri, Oct 19, 2012 at 2:45 PM, Simon Glass s...@chromium.org wrote:
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -45,6 +45,27 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
This implies every coreboot board is Intel. When you start to
introduce hardware specific U-Boot components, you need to introduce a
board specific config file.
Would it be better to have a CONFIG_X86_COREBOOT and a coreboot 'SoC'
and no coreboot board?
I am not sure about using the SOC - after all we might need that
concept soon on x86. Maybe we should create a new board config that
includes coreboot.h?
Having said that I'm not sure how important it is right now. So far,
coreboot.h is actually a particular class of boards, all Intel based.
We can name it whatever we want when we actually have other boards
which are coreboot but not Intel. Up to you
Regards,
SImon
Regards,
Graeme
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Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Simon,
On Tue, Oct 23, 2012 at 4:34 PM, Simon Glass s...@chromium.org wrote:
Hi Graeme,
On Thu, Oct 18, 2012 at 9:12 PM, Graeme Russ graeme.r...@gmail.com wrote:
Hi Simon,
On Fri, Oct 19, 2012 at 2:45 PM, Simon Glass s...@chromium.org wrote:
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -45,6 +45,27 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
This implies every coreboot board is Intel. When you start to
introduce hardware specific U-Boot components, you need to introduce a
board specific config file.
Would it be better to have a CONFIG_X86_COREBOOT and a coreboot 'SoC'
and no coreboot board?
I am not sure about using the SOC - after all we might need that
concept soon on x86. Maybe we should create a new board config that
includes coreboot.h?
SoC was the wrong abstraction - I think coreboot library is better
(see my email I just sent)
Having said that I'm not sure how important it is right now. So far,
coreboot.h is actually a particular class of boards, all Intel based.
We can name it whatever we want when we actually have other boards
which are coreboot but not Intel. Up to you
I plan on doing dev work on a AMD E350 based board 'soon'. The E350 is
already supported by coreboot, so I'm planning on getting coreboot
ported for this board and then run U-Boot from coreboot. So we can no
longer assume all coreboot boards will be Intel based.
Regards,
Graeme
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Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Graeme,
On Mon, Oct 22, 2012 at 10:38 PM, Graeme Russ graeme.r...@gmail.com wrote:
Hi Simon,
On Tue, Oct 23, 2012 at 4:34 PM, Simon Glass s...@chromium.org wrote:
Hi Graeme,
On Thu, Oct 18, 2012 at 9:12 PM, Graeme Russ graeme.r...@gmail.com wrote:
Hi Simon,
On Fri, Oct 19, 2012 at 2:45 PM, Simon Glass s...@chromium.org wrote:
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -45,6 +45,27 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
This implies every coreboot board is Intel. When you start to
introduce hardware specific U-Boot components, you need to introduce a
board specific config file.
Would it be better to have a CONFIG_X86_COREBOOT and a coreboot 'SoC'
and no coreboot board?
I am not sure about using the SOC - after all we might need that
concept soon on x86. Maybe we should create a new board config that
includes coreboot.h?
SoC was the wrong abstraction - I think coreboot library is better
(see my email I just sent)
Yes, ok. I can do a patch to move it, or do you want to? Presumably
this would come in after the patches that are already pending on the
mailing list?
Having said that I'm not sure how important it is right now. So far,
coreboot.h is actually a particular class of boards, all Intel based.
We can name it whatever we want when we actually have other boards
which are coreboot but not Intel. Up to you
I plan on doing dev work on a AMD E350 based board 'soon'. The E350 is
already supported by coreboot, so I'm planning on getting coreboot
ported for this board and then run U-Boot from coreboot. So we can no
longer assume all coreboot boards will be Intel based.
Sounds good! Shall we rename coreboot.h to something like chromebook-x86.h?
Regards,
Simon
Regards,
Graeme
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[U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -45,6 +45,27 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID2
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
/*---
* Real Time Clock Configuration
*/
--
1.7.7.3
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Re: [U-Boot] [PATCH 20/20] x86: config: Enable AHCI support for coreboot
Hi Simon,
On Fri, Oct 19, 2012 at 2:45 PM, Simon Glass s...@chromium.org wrote:
Enable AHCI driver for Intel SATA devices.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/coreboot.h | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 3df085b..968a9c5 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -45,6 +45,27 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL 1
+#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+ {PCI_VENDOR_ID_INTEL, \
+ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
This implies every coreboot board is Intel. When you start to
introduce hardware specific U-Boot components, you need to introduce a
board specific config file.
Would it be better to have a CONFIG_X86_COREBOOT and a coreboot 'SoC'
and no coreboot board?
Regards,
Graeme
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