Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On 03/20/2015 05:12 PM, Scott Wood wrote: > On Fri, 2015-03-20 at 17:08 -0700, York Sun wrote: >> >> On 03/20/2015 04:01 PM, Scott Wood wrote: >>> On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define CONFIG_DDR_CLK_FREQ 1 #define COUNTER_FREQUENCY_REAL(CONFIG_SYS_CLK_FREQ/4) >>> >>> Why? >> >> The timer clock source is not a fixed clock. It derives from system clock, >> dividing by 4. For this board, the system clock is fixed on board. But I >> don't >> think the timer clock should be hard-coded. > > I was referring to the DDR clock change. DDR reference clock is fixed on RDB. > @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RST_CTL_RESET_EN0x30 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 >>> >>> Is this really a difference between the two boards? >>> >> >> RDB is designed to be compatible in many ways to QDS, but it is still >> different. >> The QIXIS is compatible with most common registers, but not all of them. > > OK. I wasn't sure if it was just something that got added by someone > working on RDB, that also exists on QDS. > The RST_CTL_RESET_EN bit? It was enabled by default on QDS, but disable on RDB. We need to enable it in order to use "reset" command. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On Fri, 2015-03-20 at 17:08 -0700, York Sun wrote: > > On 03/20/2015 04:01 PM, Scott Wood wrote: > > On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: > >> #ifndef __ASSEMBLY__ > >> unsigned long get_board_sys_clk(void); > >> -unsigned long get_board_ddr_clk(void); > >> #endif > >> > >> #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() > >> -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() > >> +#define CONFIG_DDR_CLK_FREQ 1 > >> #define COUNTER_FREQUENCY_REAL(CONFIG_SYS_CLK_FREQ/4) > > > > Why? > > The timer clock source is not a fixed clock. It derives from system clock, > dividing by 4. For this board, the system clock is fixed on board. But I don't > think the timer clock should be hard-coded. I was referring to the DDR clock change. > >> @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); > >> #define QIXIS_LBMAP_DFLTBANK 0x00 > >> #define QIXIS_LBMAP_ALTBANK 0x04 > >> #define QIXIS_RST_CTL_RESET 0x31 > >> +#define QIXIS_RST_CTL_RESET_EN0x30 > >> #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 > >> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 > >> #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 > > > > Is this really a difference between the two boards? > > > > RDB is designed to be compatible in many ways to QDS, but it is still > different. > The QIXIS is compatible with most common registers, but not all of them. OK. I wasn't sure if it was just something that got added by someone working on RDB, that also exists on QDS. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On 03/20/2015 04:01 PM, Scott Wood wrote: > On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: >> The LS2080ARDB is a evaluation platform that supports LS2080A >> family SoCs. This patch add sbasic support for the platform. > > s/2080/2085/ > >> diff --git a/board/freescale/ls2085aqds/Makefile >> b/board/freescale/ls2085ardb/Makefile >> similarity index 81% >> copy from board/freescale/ls2085aqds/Makefile >> copy to board/freescale/ls2085ardb/Makefile >> index f174f33..0bfe21c 100644 >> --- a/board/freescale/ls2085aqds/Makefile >> +++ b/board/freescale/ls2085ardb/Makefile >> @@ -4,5 +4,5 @@ >> # SPDX-License-Identifier: GPL-2.0+ >> # >> >> -obj-y += ls2085aqds.o >> +obj-y += ls2085ardb.o >> obj-y += ddr.o >> diff --git a/board/freescale/ls2085aqds/README >> b/board/freescale/ls2085ardb/README >> similarity index 73% >> copy from board/freescale/ls2085aqds/README >> copy to board/freescale/ls2085ardb/README >> index a4d7b53..19f9d2a 100644 >> --- a/board/freescale/ls2085aqds/README >> +++ b/board/freescale/ls2085ardb/README >> @@ -1,10 +1,8 @@ >> Overview >> >> -The LS2080A Development System (QDS) is a high-performance computing, >> +The LS2080A Reference Design (RDB) is a high-performance computing, >> evaluation, and development platform that supports the QorIQ LS2080A >> -LayerScape Architecture processor. The LS2080AQDS provides validation and >> -SW development platform for the Freescale LS2080A processor series, with >> -a complete debugging environment. >> +LayerScape Architecture processor. > > I don't think Layerscape is supposed to be capitalized that way. > >> LS2085A SoC Overview >> -- >> @@ -50,14 +48,11 @@ The LS2085A SoC includes the following function and >> features: >> - Service processor (SP) provides pre-boot initialization and secure-boot >>capabilities >> >> - LS2080AQDS board Overview >> + LS2080aRDB board Overview > > Inconsistent capitalization > >> #ifndef __ASSEMBLY__ >> unsigned long get_board_sys_clk(void); >> -unsigned long get_board_ddr_clk(void); >> #endif >> >> #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() >> -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() >> +#define CONFIG_DDR_CLK_FREQ 1 >> #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) > > Why? The timer clock source is not a fixed clock. It derives from system clock, dividing by 4. For this board, the system clock is fixed on board. But I don't think the timer clock should be hard-coded. > >> @@ -30,8 +32,8 @@ unsigned long get_board_ddr_clk(void); >> #define CONFIG_MEM_INIT_VALUE 0xdeadbeef >> #define SPD_EEPROM_ADDRESS1 0x51 >> #define SPD_EEPROM_ADDRESS2 0x52 >> -#define SPD_EEPROM_ADDRESS3 0x53 >> -#define SPD_EEPROM_ADDRESS4 0x54 >> +#define SPD_EEPROM_ADDRESS3 0x54 >> +#define SPD_EEPROM_ADDRESS4 0x53/* Bard error */ >> #define SPD_EEPROM_ADDRESS5 0x55 >> #define SPD_EEPROM_ADDRESS6 0x56/* dummy address */ >> #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 > > I suspect this should be s/Bard/Board/ Right. > >> @@ -114,24 +106,24 @@ unsigned long get_board_ddr_clk(void); >> | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ >> | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ >> | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ >> -| CSOR_NAND_PGS_2K /* Page Size = 2K */ \ >> -| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ >> -| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ >> +| CSOR_NAND_PGS_4K /* Page Size = 2K */ \ >> +| CSOR_NAND_SPRZ_224/* Spare size = 64 */ \ >> +| CSOR_NAND_PB(128))/*Pages Per Block = 64*/ > > Comments don't match code. Result of squashing. Will fix in next version. > >> @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); >> #define QIXIS_LBMAP_DFLTBANK0x00 >> #define QIXIS_LBMAP_ALTBANK 0x04 >> #define QIXIS_RST_CTL_RESET 0x31 >> +#define QIXIS_RST_CTL_RESET_EN 0x30 >> #define QIXIS_RCFG_CTL_RECONFIG_IDLE0x20 >> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 >> #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 > > Is this really a difference between the two boards? > RDB is designed to be compatible in many ways to QDS, but it is still different. The QIXIS is compatible with most common registers, but not all of them. I will send out a new version soon. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: > The LS2080ARDB is a evaluation platform that supports LS2080A > family SoCs. This patch add sbasic support for the platform. s/2080/2085/ > diff --git a/board/freescale/ls2085aqds/Makefile > b/board/freescale/ls2085ardb/Makefile > similarity index 81% > copy from board/freescale/ls2085aqds/Makefile > copy to board/freescale/ls2085ardb/Makefile > index f174f33..0bfe21c 100644 > --- a/board/freescale/ls2085aqds/Makefile > +++ b/board/freescale/ls2085ardb/Makefile > @@ -4,5 +4,5 @@ > # SPDX-License-Identifier: GPL-2.0+ > # > > -obj-y += ls2085aqds.o > +obj-y += ls2085ardb.o > obj-y += ddr.o > diff --git a/board/freescale/ls2085aqds/README > b/board/freescale/ls2085ardb/README > similarity index 73% > copy from board/freescale/ls2085aqds/README > copy to board/freescale/ls2085ardb/README > index a4d7b53..19f9d2a 100644 > --- a/board/freescale/ls2085aqds/README > +++ b/board/freescale/ls2085ardb/README > @@ -1,10 +1,8 @@ > Overview > > -The LS2080A Development System (QDS) is a high-performance computing, > +The LS2080A Reference Design (RDB) is a high-performance computing, > evaluation, and development platform that supports the QorIQ LS2080A > -LayerScape Architecture processor. The LS2080AQDS provides validation and > -SW development platform for the Freescale LS2080A processor series, with > -a complete debugging environment. > +LayerScape Architecture processor. I don't think Layerscape is supposed to be capitalized that way. > LS2085A SoC Overview > -- > @@ -50,14 +48,11 @@ The LS2085A SoC includes the following function and > features: > - Service processor (SP) provides pre-boot initialization and secure-boot >capabilities > > - LS2080AQDS board Overview > + LS2080aRDB board Overview Inconsistent capitalization > #ifndef __ASSEMBLY__ > unsigned long get_board_sys_clk(void); > -unsigned long get_board_ddr_clk(void); > #endif > > #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() > -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() > +#define CONFIG_DDR_CLK_FREQ 1 > #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) Why? > @@ -30,8 +32,8 @@ unsigned long get_board_ddr_clk(void); > #define CONFIG_MEM_INIT_VALUE0xdeadbeef > #define SPD_EEPROM_ADDRESS1 0x51 > #define SPD_EEPROM_ADDRESS2 0x52 > -#define SPD_EEPROM_ADDRESS3 0x53 > -#define SPD_EEPROM_ADDRESS4 0x54 > +#define SPD_EEPROM_ADDRESS3 0x54 > +#define SPD_EEPROM_ADDRESS4 0x53/* Bard error */ > #define SPD_EEPROM_ADDRESS5 0x55 > #define SPD_EEPROM_ADDRESS6 0x56/* dummy address */ > #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 I suspect this should be s/Bard/Board/ > @@ -114,24 +106,24 @@ unsigned long get_board_ddr_clk(void); > | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ > | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ > | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ > - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ > - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ > - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ > + | CSOR_NAND_PGS_4K /* Page Size = 2K */ \ > + | CSOR_NAND_SPRZ_224/* Spare size = 64 */ \ > + | CSOR_NAND_PB(128))/*Pages Per Block = 64*/ Comments don't match code. > @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); > #define QIXIS_LBMAP_DFLTBANK 0x00 > #define QIXIS_LBMAP_ALTBANK 0x04 > #define QIXIS_RST_CTL_RESET 0x31 > +#define QIXIS_RST_CTL_RESET_EN 0x30 > #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 > #define QIXIS_RCFG_CTL_RECONFIG_START0x21 > #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE0x08 Is this really a difference between the two boards? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform
The LS2080ARDB is a evaluation platform that supports LS2080A
family SoCs. This patch add sbasic support for the platform.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Bhupesh Sharma
Signed-off-by: Scott Wood
Change-Id: I7744b17f074488989de998ab7d487c437cc8eedf
---
arch/arm/Kconfig | 11 +++
arch/arm/cpu/armv8/fsl-lsch3/README|4 +-
board/freescale/{ls2085aqds => ls2085ardb}/Kconfig |6 +-
board/freescale/ls2085ardb/MAINTAINERS |7 ++
.../freescale/{ls2085aqds => ls2085ardb}/Makefile |2 +-
board/freescale/{ls2085aqds => ls2085ardb}/README | 46
board/freescale/{ls2085aqds => ls2085ardb}/ddr.c |0
board/freescale/{ls2085aqds => ls2085ardb}/ddr.h |6 +-
.../ls2085aqds.c => ls2085ardb/ls2085ardb.c} | 54 +++
.../ls2085ardb_qixis.h}| 12 +---
...qds_ddr4_nor_defconfig => ls2085ardb_defconfig} |2 +-
include/configs/{ls2085aqds.h => ls2085ardb.h} | 73
12 files changed, 80 insertions(+), 143 deletions(-)
copy board/freescale/{ls2085aqds => ls2085ardb}/Kconfig (66%)
create mode 100644 board/freescale/ls2085ardb/MAINTAINERS
copy board/freescale/{ls2085aqds => ls2085ardb}/Makefile (81%)
copy board/freescale/{ls2085aqds => ls2085ardb}/README (73%)
copy board/freescale/{ls2085aqds => ls2085ardb}/ddr.c (100%)
copy board/freescale/{ls2085aqds => ls2085ardb}/ddr.h (93%)
copy board/freescale/{ls2085aqds/ls2085aqds.c => ls2085ardb/ls2085ardb.c} (76%)
copy board/freescale/{ls2085aqds/ls2085aqds_qixis.h =>
ls2085ardb/ls2085ardb_qixis.h} (61%)
copy configs/{ls1021aqds_ddr4_nor_defconfig => ls2085ardb_defconfig} (66%)
copy include/configs/{ls2085aqds.h => ls2085ardb.h} (80%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f4a7851..7478eb4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -658,6 +658,16 @@ config TARGET_LS2085AQDS
development platform that supports the QorIQ LS2085A
Layerscape Architecture processor.
+config TARGET_LS2085ARDB
+ bool "Support ls2085ardb"
+ select ARM64
+ select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2085ARDB platform.
+ The LS2080A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2085A
+ LayerScape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -804,6 +814,7 @@ source "board/embest/mx6boards/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
+source "board/freescale/ls2085ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/mx23evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-lsch3/README
index 817ea1b..4f36e2a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -38,7 +38,7 @@ Flash Layout
32-MB NOR flash layout for pre-silicon platforms (simulator and
emulator)
(2) A typical layout of various images (including Linux and other firmware
images)
-is shown below considering a 128MB NOR flash device present on QDS
+is shown below considering a 128MB NOR flash device present on QDS and RDB
boards:
- > 0x5_8800_ ---
| .. Unused .. (7M) | |
@@ -86,7 +86,7 @@ Flash Layout
| RCW and PBI (1M)| |
- > 0x5_8000_ ---
- 128-MB NOR flash layout for QDS board
+ 128-MB NOR flash layout for QDS and RDB boards
Environment Variables
=
diff --git a/board/freescale/ls2085aqds/Kconfig
b/board/freescale/ls2085ardb/Kconfig
similarity index 66%
copy from board/freescale/ls2085aqds/Kconfig
copy to board/freescale/ls2085ardb/Kconfig
index deb640d..85a3dcd 100644
--- a/board/freescale/ls2085aqds/Kconfig
+++ b/board/freescale/ls2085ardb/Kconfig
@@ -1,8 +1,8 @@
-if TARGET_LS2085AQDS
+if TARGET_LS2085ARDB
config SYS_BOARD
- default "ls2085aqds"
+ default "ls2085ardb"
config SYS_VENDOR
default "freescale"
@@ -11,6 +11,6 @@ config SYS_SOC
default "fsl-lsch3"
config SYS_CONFIG_NAME
- default "ls2085aqds"
+ default "ls2085ardb"
endif
diff --git a/board/freescale/ls2085ardb/MAINTAINERS
b/board/freescale/ls2085ardb/MAINTAINERS
new file mode 100644
index 000..436039f
--- /dev/null
+++ b/board/freescale/ls2085ardb/MAINTAINERS
@@ -0,0 +1,7 @@
+LS2085A BOARD
+M: Prabhakar Kushwaha
+S: Maintained
+F: board/freescale/ls2085ardb/
+F: board/freescale/ls2085a/ls2085ardb.c
+F: include/configs/ls2085ardb.h
+F:
