The clk_divider must be set to 1 on ddr52 8bit mode for rockchip
platform. Otherwise we will get a data crc error during data
transmission.
Signed-off-by: Ziyuan Xu <xzy...@rock-chips.com>
---
drivers/mmc/dw_mmc.c | 2 +-
drivers/mmc/rockchip_dw_mmc.c | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index e862eb2..dcd7fba 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -344,7 +344,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
int timeout = 10000;
unsigned long sclk;
- if ((freq == host->clock) || (freq == 0))
+ if (freq == 0)
return 0;
/*
* If host->get_mmc_clk isn't defined,
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 474ca1c..b2b7f5a 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -43,6 +43,13 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host
*host, uint freq)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
int ret;
+ /*
+ * If DDR52 8bit mode(only emmc work in 8bit mode),
+ * divider must be set 1
+ */
+ if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8)
+ freq *= 2;
+
ret = clk_set_rate(&priv->clk, freq);
if (ret < 0) {
printf("%s: err=%d\n", __func__, ret);
--
2.7.4
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