Re: [U-Boot] [PATCH 3/3] mvebu: dts: a80x0: Sync the DB DTS with standard config A

2017-03-30 Thread Stefan Roese 

On 28.03.2017 17:36, kos...@marvell.com wrote:

From: Konstantin Porotchkin 

Sync the default configuration of Armada-8040-DB with
Marvell u-boot-2015  standard configuration "A" for the same board.
The standard configuration "A" enables 2 PCIe slots on CP0
and 3 PCIe slots on CP1.
This is the main configuration used for u-boot  and Linux tests.
This patch also re-arranges the DTS file entries by grouping
all nodes related to CP0 and CP1.

Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Igal Liberman 
Cc: Nadav Haklai 
---
 arch/arm/dts/armada-8040-db.dts | 222 +---
 1 file changed, 115 insertions(+), 107 deletions(-)

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 40def9d..e1e6dfd 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -83,28 +83,68 @@

 _pinctl {
/* MPP Bus:
-* [0-31] = 0xff: Keep default CP0_shared_pins:
-* [11] CLKOUT_MPP_11 (out)
-* [23] LINK_RD_IN_CP2CP (in)
-* [25] CLKOUT_MPP_25 (out)
-* [29] AVS_FB_IN_CP2CP (in)
-* [32,34] SMI
-* [31]GPIO: push button/Wake
-* [35-36] GPIO
-* [37-38] I2C
-* [40-41] SATA[0/1]_PRESENT_ACTIVEn
-* [42-43] XSMI
-* [44-55] RGMII1
-* [56-62] SD
+*  [0-31]  = 0xff: Keep default CP0_shared_pins
+*  [11]CLKOUT_MPP_11 (out)
+*  [23]LINK_RD_IN_CP2CP (in)
+*  [25]CLKOUT_MPP_25 (out)
+*  [29]AVS_FB_IN_CP2CP (in)
+*  [32,34] GE_MDIO/MDC
+*  [33]GPIO: GE_INT#/push button/Wake
+*  [35]MSS_GPIO[3]: MSS_PWDN
+*  [36]MSS_GPIO[5]: MSS_VTT_EN
+*  [37-38] I2C0
+*  [39]PTP_CLK
+*  [40-41] SATA[0/1]_PRESENT_ACTIVEn
+*  [42-43] XG_MDC/XG_MDIO (XSMI)
+*  [44-55] RGMII1
+*  [56-62] SD
 */
-   /*   0123456789 */
+   /*   0123456789 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
-0xff 070700220
-0088111111
-1111110xe  0xe  0xe  0xe
-0xe  0xe  0xe >;
+0xff 0xff 0x7  0x0  0x7  0xa  0xa  0x2  0x2  0x5
+0x9  0x9  0x8  0x8  0x1  0x1  0x1  0x1  0x1  0x1
+0x1  0x1  0x1  0x1  0x1  0x1  0xe  0xe  0xe  0xe
+0xe  0xe  0xe>;
+};
+
+_comphy {
+   /* Serdes Configuration:
+*  Lane 0: PCIe0 (x1)
+*  Lane 1: SATA0
+*  Lane 2: KR (10G)
+*  Lane 3: SATA1
+*  Lane 4: USB3_HOST1
+*  Lane 5: PCIe2 (x1)
+*/
+   phy0 {
+   phy-type = ;
+   };
+   phy1 {
+   phy-type = ;
+   };
+   phy2 {
+   phy-type = ;
+   };
+   phy3 {
+   phy-type = ;
+   };
+   phy4 {
+   phy-type = ;
+   };
+   phy5 {
+   phy-type = ;
+   };
+};
+
+/* CON6 on CP0 expansion */
+_pcie0 {
+   status = "okay";
+};
+
+_pcie1 {
+   status = "disabled";
 };

 /* CON5 on CP0 expansion */
@@ -134,21 +174,69 @@
status = "okay";
 };

+_utmi0 {
+   status = "okay";
+};
+
+_utmi1 {
+   status = "okay";
+};
+
 _pinctl {
/* MPP Bus:
-* [0-11]  RGMII0
-* [13-16] SPI1
-* [27,31] GE_MDIO/MDC
-* [32-62] = 0xff: Keep default CP1_shared_pins:
+*  [0-11]  RGMII0
+*  [13-16] SPI1
+*  [27,31] GE_MDIO/MDC
+*  [28]SATA1_PRESENT_ACTIVEn
+*  [29-30] UART0
+*  [32-62] = 0xff: Keep default CP1_shared_pins
 */
-   /*   0123456789 */
+   /*   0123456789 */
pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
-0x3  0x3  0xff 0x3  0x3  0x3  0x3  0xff 0xff 0xff
-0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0xff 0xff
-0xff 0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0x3  0x3  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
+0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0x9  0xa
+0xA  0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
-

[U-Boot] [PATCH 3/3] mvebu: dts: a80x0: Sync the DB DTS with standard config A

2017-03-28 Thread kostap 
From: Konstantin Porotchkin 

Sync the default configuration of Armada-8040-DB with
Marvell u-boot-2015  standard configuration "A" for the same board.
The standard configuration "A" enables 2 PCIe slots on CP0
and 3 PCIe slots on CP1.
This is the main configuration used for u-boot  and Linux tests.
This patch also re-arranges the DTS file entries by grouping
all nodes related to CP0 and CP1.

Signed-off-by: Konstantin Porotchkin 
Cc: Stefan Roese 
Cc: Igal Liberman 
Cc: Nadav Haklai 
---
 arch/arm/dts/armada-8040-db.dts | 222 +---
 1 file changed, 115 insertions(+), 107 deletions(-)

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 40def9d..e1e6dfd 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -83,28 +83,68 @@
 
 _pinctl {
/* MPP Bus:
-* [0-31] = 0xff: Keep default CP0_shared_pins:
-* [11] CLKOUT_MPP_11 (out)
-* [23] LINK_RD_IN_CP2CP (in)
-* [25] CLKOUT_MPP_25 (out)
-* [29] AVS_FB_IN_CP2CP (in)
-* [32,34] SMI
-* [31]GPIO: push button/Wake
-* [35-36] GPIO
-* [37-38] I2C
-* [40-41] SATA[0/1]_PRESENT_ACTIVEn
-* [42-43] XSMI
-* [44-55] RGMII1
-* [56-62] SD
+*  [0-31]  = 0xff: Keep default CP0_shared_pins
+*  [11]CLKOUT_MPP_11 (out)
+*  [23]LINK_RD_IN_CP2CP (in)
+*  [25]CLKOUT_MPP_25 (out)
+*  [29]AVS_FB_IN_CP2CP (in)
+*  [32,34] GE_MDIO/MDC
+*  [33]GPIO: GE_INT#/push button/Wake
+*  [35]MSS_GPIO[3]: MSS_PWDN
+*  [36]MSS_GPIO[5]: MSS_VTT_EN
+*  [37-38] I2C0
+*  [39]PTP_CLK
+*  [40-41] SATA[0/1]_PRESENT_ACTIVEn
+*  [42-43] XG_MDC/XG_MDIO (XSMI)
+*  [44-55] RGMII1
+*  [56-62] SD
 */
-   /*   0123456789 */
+   /*   0123456789 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
-0xff 070700220
-0088111111
-1111110xe  0xe  0xe  0xe
-0xe  0xe  0xe >;
+0xff 0xff 0x7  0x0  0x7  0xa  0xa  0x2  0x2  0x5
+0x9  0x9  0x8  0x8  0x1  0x1  0x1  0x1  0x1  0x1
+0x1  0x1  0x1  0x1  0x1  0x1  0xe  0xe  0xe  0xe
+0xe  0xe  0xe>;
+};
+
+_comphy {
+   /* Serdes Configuration:
+*  Lane 0: PCIe0 (x1)
+*  Lane 1: SATA0
+*  Lane 2: KR (10G)
+*  Lane 3: SATA1
+*  Lane 4: USB3_HOST1
+*  Lane 5: PCIe2 (x1)
+*/
+   phy0 {
+   phy-type = ;
+   };
+   phy1 {
+   phy-type = ;
+   };
+   phy2 {
+   phy-type = ;
+   };
+   phy3 {
+   phy-type = ;
+   };
+   phy4 {
+   phy-type = ;
+   };
+   phy5 {
+   phy-type = ;
+   };
+};
+
+/* CON6 on CP0 expansion */
+_pcie0 {
+   status = "okay";
+};
+
+_pcie1 {
+   status = "disabled";
 };
 
 /* CON5 on CP0 expansion */
@@ -134,21 +174,69 @@
status = "okay";
 };
 
+_utmi0 {
+   status = "okay";
+};
+
+_utmi1 {
+   status = "okay";
+};
+
 _pinctl {
/* MPP Bus:
-* [0-11]  RGMII0
-* [13-16] SPI1
-* [27,31] GE_MDIO/MDC
-* [32-62] = 0xff: Keep default CP1_shared_pins:
+*  [0-11]  RGMII0
+*  [13-16] SPI1
+*  [27,31] GE_MDIO/MDC
+*  [28]SATA1_PRESENT_ACTIVEn
+*  [29-30] UART0
+*  [32-62] = 0xff: Keep default CP1_shared_pins
 */
-   /*   0123456789 */
+   /*   0123456789 */
pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
-0x3  0x3  0xff 0x3  0x3  0x3  0x3  0xff 0xff 0xff
-0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0xff 0xff
-0xff 0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+0x3  0x3  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
+0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0x9  0xa
+0xA  0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
-0xff 0xff 0xff >;
+