subject:"\[U\-Boot\] \[PATCH 3\/4\] EXYNOS\: additional Exynos4 SoC series support"

Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

2012-10-09 Thread Minkyu Kang

Dear Jeong-Hyeon Kim,

On 29 August 2012 12:28,   wrote:
> From: Jeong-Hyeon Kim 
>
> - Fixed MPLL register address
>   It's different between Exynos4210 and Exynos4412.
>
> - Added pinmux functions for Exynos4
>
> - Added extended gpios for Exynos4412
>   Exynos4412 has more gpios than Exynos4210.
>
> Signed-off-by: Jeong-Hyeon Kim 
> ---
>  arch/arm/cpu/armv7/exynos/clock.c|   67 
>  arch/arm/cpu/armv7/exynos/pinmux.c   |  241 
> ++
>  arch/arm/include/asm/arch-exynos/clock.h |  240 +
>  arch/arm/include/asm/arch-exynos/cpu.h   |   14 ++-
>  arch/arm/include/asm/arch-exynos/gpio.h  |   21 +++-
>  5 files changed, 578 insertions(+), 5 deletions(-)
>
>

Chander posted similar patch for support the exynos4x12.
So, please kindly check his patch and update your patch.

http://patchwork.ozlabs.org/patch/188437/
http://patchwork.ozlabs.org/patch/188438/
http://patchwork.ozlabs.org/patch/188511/
http://patchwork.ozlabs.org/patch/188512/
http://patchwork.ozlabs.org/patch/188513/
http://patchwork.ozlabs.org/patch/189809/

Thanks.
Minkyu Kang.
-- 
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www.promsoft.net
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Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

2012-08-28 Thread snow . jhkim

From: Jeong-Hyeon Kim 

- Fixed MPLL register address
  It's different between Exynos4210 and Exynos4412.

- Added pinmux functions for Exynos4

- Added extended gpios for Exynos4412
  Exynos4412 has more gpios than Exynos4210.

Signed-off-by: Jeong-Hyeon Kim 
---
 arch/arm/cpu/armv7/exynos/clock.c|   67 
 arch/arm/cpu/armv7/exynos/pinmux.c   |  241 ++
 arch/arm/include/asm/arch-exynos/clock.h |  240 +
 arch/arm/include/asm/arch-exynos/cpu.h   |   14 ++-
 arch/arm/include/asm/arch-exynos/gpio.h  |   21 +++-
 5 files changed, 578 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
b/arch/arm/cpu/armv7/exynos/clock.c
index 680aeeb..002a493 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -92,6 +92,70 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
return fout;
 }
 
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4412_get_pll_clk(int pllreg)
+{
+   struct exynos4412_clock *clk =
+   (struct exynos4412_clock *)samsung_get_base_clock();
+   unsigned long r, m, p, s, k = 0, mask, fout;
+   unsigned int freq;
+
+   switch (pllreg) {
+   case APLL:
+   r = readl(&clk->apll_con0);
+   break;
+   case MPLL:
+   r = readl(&clk->mpll_con0);
+   break;
+   case EPLL:
+   r = readl(&clk->epll_con0);
+   k = readl(&clk->epll_con1);
+   break;
+   case VPLL:
+   r = readl(&clk->vpll_con0);
+   k = readl(&clk->vpll_con1);
+   break;
+   default:
+   printf("Unsupported PLL (%d)\n", pllreg);
+   return 0;
+   }
+
+   /*
+* APLL_CON: MIDV [25:16]
+* MPLL_CON: MIDV [25:16]
+* EPLL_CON: MIDV [24:16]
+* VPLL_CON: MIDV [24:16]
+*/
+   if (pllreg == APLL || pllreg == MPLL)
+   mask = 0x3ff;
+   else
+   mask = 0x1ff;
+
+   m = (r >> 16) & mask;
+
+   /* PDIV [13:8] */
+   p = (r >> 8) & 0x3f;
+   /* SDIV [2:0] */
+   s = r & 0x7;
+
+   freq = CONFIG_SYS_CLK_FREQ;
+
+   if (pllreg == EPLL) {
+   k = k & 0x;
+   /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+   fout = (m + k / 65536) * (freq / (p * (1 << s)));
+   } else if (pllreg == VPLL) {
+   k = k & 0x;
+   /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+   fout = (m + k / 65536) * (freq / (p * (1 << s)));
+   } else {
+   /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+   fout = m * (freq / (p * (1 << s)));
+   }
+
+   return fout;
+}
+
 /* exynos5: return pll clock frequency */
 static unsigned long exynos5_get_pll_clk(int pllreg)
 {
@@ -745,6 +809,9 @@ unsigned long get_pll_clk(int pllreg)
if (cpu_is_exynos5())
return exynos5_get_pll_clk(pllreg);
else
+   if (cpu_is_exynos4412())
+   return exynos4412_get_pll_clk(pllreg);
+   else
return exynos4_get_pll_clk(pllreg);
 }
 
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 7776add..0746878 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -26,6 +26,245 @@
 #include 
 #include 
 
+static void exynos4_uart_config(int peripheral)
+{
+   struct exynos4_gpio_part1 *gpio1 =
+   (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+   struct s5p_gpio_bank *bank;
+   int i, start, count;
+
+   switch (peripheral) {
+   case PERIPH_ID_UART0:
+   bank = &gpio1->a0;
+   start = 0;
+   count = 4;
+   break;
+   case PERIPH_ID_UART1:
+   bank = &gpio1->a0;
+   start = 4;
+   count = 4;
+   break;
+   case PERIPH_ID_UART2:
+   bank = &gpio1->a1;
+   start = 0;
+   count = 4;
+   break;
+   case PERIPH_ID_UART3:
+   bank = &gpio1->a1;
+   start = 4;
+   count = 2;
+   break;
+   }
+   for (i = start; i < start + count; i++) {
+   s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+   }
+}
+
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+   struct exynos4_gpio_part2 *gpio2 =
+   (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
+   struct s5p_gpio_bank *bank, *bank_ext;
+   int i, start = 0, gpio_func = 0;
+
+   switch (peripheral) {
+   case PERIPH_ID_SDMMC0:
+   bank = &gpio2->k0;
+   bank_ext = &gpio2->k1;
+   start = 3;
+   gpio_func = GPIO_FUNC(0x2);
+

Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

2012-08-28 Thread Minkyu Kang

On 29 August 2012 09:23, Kyungmin Park  wrote:
> Hi,
>
> On 8/28/12, snow.jh...@gmail.com  wrote:
>> From: Jeong-Hyeon Kim 
>>
>> - Fixed MPLL register address
>>   It's different between Exynos4210 and Exynos4412.
>>
>> - Added pinmux functions for Exynos4
>>
>> - Added extended gpios for Exynos4412
>>   Exynos4412 has more gpios than Exynos4210.
>>
>> Signed-off-by: Jeong-Hyeon Kim 
>> ---
>>  arch/arm/cpu/armv7/exynos/clock.c|   11 ++
>>  arch/arm/cpu/armv7/exynos/pinmux.c   |  241
>> ++
>>  arch/arm/include/asm/arch-exynos/clock.h |   27 
>>  arch/arm/include/asm/arch-exynos/cpu.h   |4 +
>>  arch/arm/include/asm/arch-exynos/gpio.h  |   21 +++-
>>  5 files changed, 303 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
>> b/arch/arm/cpu/armv7/exynos/clock.c
>> index 680aeeb..84a6725 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -79,14 +79,25 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
>>   /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
>>   fout = (m + k / 65536) * (freq / (p * (1 << s)));
>>   } else if (pllreg == VPLL) {
>> +#ifdef CONFIG_EXYNOS4210
> we don't like the ifdefy at here. How about to check soc_is_4210 and
> soc_is_4412?
>>   k = k & 0xfff;
>>   /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
>>   fout = (m + k / 1024) * (freq / (p * (1 << s)));
>> +#else
>> + k = k & 0x;
>> + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
>> + fout = (m + k / 65536) * (freq / (p * (1 << s)));
>> +#endif
>>   } else {
>> +#ifdef CONFIG_EXYNOS4210
> ditto
>>   if (s < 1)
>>   s = 1;
>>   /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
>>   fout = m * (freq / (p * (1 << (s - 1;
>> +#else
>> + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
>> + fout = m * (freq / (p * (1 << s)));
>> +#endif
>>   }
>>
>>   return fout;
>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>> index 7776add..0746878 100644
>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>> @@ -26,6 +26,245 @@
>>  #include 
>>  #include 
>>
>> +static void exynos4_uart_config(int peripheral)
>> +{
>> + struct exynos4_gpio_part1 *gpio1 =
>> + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
>> + struct s5p_gpio_bank *bank;
>> + int i, start, count;
>> +
>> + switch (peripheral) {
>> + case PERIPH_ID_UART0:
>> + bank = &gpio1->a0;
>> + start = 0;
>> + count = 4;
>> + break;
>> + case PERIPH_ID_UART1:
>> + bank = &gpio1->a0;
>> + start = 4;
>> + count = 4;
>> + break;
>> + case PERIPH_ID_UART2:
>> + bank = &gpio1->a1;
>> + start = 0;
>> + count = 4;
>> + break;
>> + case PERIPH_ID_UART3:
>> + bank = &gpio1->a1;
>> + start = 4;
>> + count = 2;
>> + break;
>> + }
>> + for (i = start; i < start + count; i++) {
>> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
>> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>> + }
>> +}
>> +
>> +static int exynos4_mmc_config(int peripheral, int flags)
>> +{
>> + struct exynos4_gpio_part2 *gpio2 =
>> + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
>> + struct s5p_gpio_bank *bank, *bank_ext;
>> + int i, start = 0, gpio_func = 0;
>> +
>> + switch (peripheral) {
>> + case PERIPH_ID_SDMMC0:
>> + bank = &gpio2->k0;
>> + bank_ext = &gpio2->k1;
>> + start = 3;
>> + gpio_func = GPIO_FUNC(0x2);
>> + break;
>> + case PERIPH_ID_SDMMC1:
>> + bank = &gpio2->k1;
>> + bank_ext = NULL;
>> + break;
>> + case PERIPH_ID_SDMMC2:
>> + bank = &gpio2->k2;
>> + bank_ext = &gpio2->k3;
>> + start = 3;
>> + gpio_func = GPIO_FUNC(0x3);
>> + break;
>> + case PERIPH_ID_SDMMC3:
>> + bank = &gpio2->k3;
>> + bank_ext = NULL;
>> + break;
>> + }
>> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
>> + debug("SDMMC device %d does not support 8bit mode",
>> + peripheral);
>> + return -1;
>> + }
>> + if (flags & PINMUX_FLAG_8BIT_MODE) {
>> + for (i = start; i <= (start + 3); i++) {
>> + s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
>> + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
>> + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
>> + }
>> + }
>>

Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

2012-08-28 Thread Kyungmin Park

Hi,

On 8/28/12, snow.jh...@gmail.com  wrote:
> From: Jeong-Hyeon Kim 
>
> - Fixed MPLL register address
>   It's different between Exynos4210 and Exynos4412.
>
> - Added pinmux functions for Exynos4
>
> - Added extended gpios for Exynos4412
>   Exynos4412 has more gpios than Exynos4210.
>
> Signed-off-by: Jeong-Hyeon Kim 
> ---
>  arch/arm/cpu/armv7/exynos/clock.c|   11 ++
>  arch/arm/cpu/armv7/exynos/pinmux.c   |  241
> ++
>  arch/arm/include/asm/arch-exynos/clock.h |   27 
>  arch/arm/include/asm/arch-exynos/cpu.h   |4 +
>  arch/arm/include/asm/arch-exynos/gpio.h  |   21 +++-
>  5 files changed, 303 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 680aeeb..84a6725 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -79,14 +79,25 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
>   /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
>   fout = (m + k / 65536) * (freq / (p * (1 << s)));
>   } else if (pllreg == VPLL) {
> +#ifdef CONFIG_EXYNOS4210
we don't like the ifdefy at here. How about to check soc_is_4210 and
soc_is_4412?
>   k = k & 0xfff;
>   /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
>   fout = (m + k / 1024) * (freq / (p * (1 << s)));
> +#else
> + k = k & 0x;
> + /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
> + fout = (m + k / 65536) * (freq / (p * (1 << s)));
> +#endif
>   } else {
> +#ifdef CONFIG_EXYNOS4210
ditto
>   if (s < 1)
>   s = 1;
>   /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
>   fout = m * (freq / (p * (1 << (s - 1;
> +#else
> + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
> + fout = m * (freq / (p * (1 << s)));
> +#endif
>   }
>
>   return fout;
> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> b/arch/arm/cpu/armv7/exynos/pinmux.c
> index 7776add..0746878 100644
> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> @@ -26,6 +26,245 @@
>  #include 
>  #include 
>
> +static void exynos4_uart_config(int peripheral)
> +{
> + struct exynos4_gpio_part1 *gpio1 =
> + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
> + struct s5p_gpio_bank *bank;
> + int i, start, count;
> +
> + switch (peripheral) {
> + case PERIPH_ID_UART0:
> + bank = &gpio1->a0;
> + start = 0;
> + count = 4;
> + break;
> + case PERIPH_ID_UART1:
> + bank = &gpio1->a0;
> + start = 4;
> + count = 4;
> + break;
> + case PERIPH_ID_UART2:
> + bank = &gpio1->a1;
> + start = 0;
> + count = 4;
> + break;
> + case PERIPH_ID_UART3:
> + bank = &gpio1->a1;
> + start = 4;
> + count = 2;
> + break;
> + }
> + for (i = start; i < start + count; i++) {
> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + }
> +}
> +
> +static int exynos4_mmc_config(int peripheral, int flags)
> +{
> + struct exynos4_gpio_part2 *gpio2 =
> + (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
> + struct s5p_gpio_bank *bank, *bank_ext;
> + int i, start = 0, gpio_func = 0;
> +
> + switch (peripheral) {
> + case PERIPH_ID_SDMMC0:
> + bank = &gpio2->k0;
> + bank_ext = &gpio2->k1;
> + start = 3;
> + gpio_func = GPIO_FUNC(0x2);
> + break;
> + case PERIPH_ID_SDMMC1:
> + bank = &gpio2->k1;
> + bank_ext = NULL;
> + break;
> + case PERIPH_ID_SDMMC2:
> + bank = &gpio2->k2;
> + bank_ext = &gpio2->k3;
> + start = 3;
> + gpio_func = GPIO_FUNC(0x3);
> + break;
> + case PERIPH_ID_SDMMC3:
> + bank = &gpio2->k3;
> + bank_ext = NULL;
> + break;
> + }
> + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
> + debug("SDMMC device %d does not support 8bit mode",
> + peripheral);
> + return -1;
> + }
> + if (flags & PINMUX_FLAG_8BIT_MODE) {
> + for (i = start; i <= (start + 3); i++) {
> + s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
> + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
> + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
> + }
> + }
> + for (i = 0; i < 2; i++) {
> + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
> + s5p_gpio_set_drv(bank, i, G

[U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

2012-08-28 Thread snow . jhkim

From: Jeong-Hyeon Kim 

- Fixed MPLL register address
  It's different between Exynos4210 and Exynos4412.

- Added pinmux functions for Exynos4

- Added extended gpios for Exynos4412
  Exynos4412 has more gpios than Exynos4210.

Signed-off-by: Jeong-Hyeon Kim 
---
 arch/arm/cpu/armv7/exynos/clock.c|   11 ++
 arch/arm/cpu/armv7/exynos/pinmux.c   |  241 ++
 arch/arm/include/asm/arch-exynos/clock.h |   27 
 arch/arm/include/asm/arch-exynos/cpu.h   |4 +
 arch/arm/include/asm/arch-exynos/gpio.h  |   21 +++-
 5 files changed, 303 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
b/arch/arm/cpu/armv7/exynos/clock.c
index 680aeeb..84a6725 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -79,14 +79,25 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 65536) * (freq / (p * (1 << s)));
} else if (pllreg == VPLL) {
+#ifdef CONFIG_EXYNOS4210
k = k & 0xfff;
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 1024) * (freq / (p * (1 << s)));
+#else
+   k = k & 0x;
+   /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+   fout = (m + k / 65536) * (freq / (p * (1 << s)));
+#endif
} else {
+#ifdef CONFIG_EXYNOS4210
if (s < 1)
s = 1;
/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
fout = m * (freq / (p * (1 << (s - 1;
+#else
+   /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+   fout = m * (freq / (p * (1 << s)));
+#endif
}
 
return fout;
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 7776add..0746878 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -26,6 +26,245 @@
 #include 
 #include 
 
+static void exynos4_uart_config(int peripheral)
+{
+   struct exynos4_gpio_part1 *gpio1 =
+   (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+   struct s5p_gpio_bank *bank;
+   int i, start, count;
+
+   switch (peripheral) {
+   case PERIPH_ID_UART0:
+   bank = &gpio1->a0;
+   start = 0;
+   count = 4;
+   break;
+   case PERIPH_ID_UART1:
+   bank = &gpio1->a0;
+   start = 4;
+   count = 4;
+   break;
+   case PERIPH_ID_UART2:
+   bank = &gpio1->a1;
+   start = 0;
+   count = 4;
+   break;
+   case PERIPH_ID_UART3:
+   bank = &gpio1->a1;
+   start = 4;
+   count = 2;
+   break;
+   }
+   for (i = start; i < start + count; i++) {
+   s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+   }
+}
+
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+   struct exynos4_gpio_part2 *gpio2 =
+   (struct exynos4_gpio_part2 *) samsung_get_base_gpio_part2();
+   struct s5p_gpio_bank *bank, *bank_ext;
+   int i, start = 0, gpio_func = 0;
+
+   switch (peripheral) {
+   case PERIPH_ID_SDMMC0:
+   bank = &gpio2->k0;
+   bank_ext = &gpio2->k1;
+   start = 3;
+   gpio_func = GPIO_FUNC(0x2);
+   break;
+   case PERIPH_ID_SDMMC1:
+   bank = &gpio2->k1;
+   bank_ext = NULL;
+   break;
+   case PERIPH_ID_SDMMC2:
+   bank = &gpio2->k2;
+   bank_ext = &gpio2->k3;
+   start = 3;
+   gpio_func = GPIO_FUNC(0x3);
+   break;
+   case PERIPH_ID_SDMMC3:
+   bank = &gpio2->k3;
+   bank_ext = NULL;
+   break;
+   }
+   if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+   debug("SDMMC device %d does not support 8bit mode",
+   peripheral);
+   return -1;
+   }
+   if (flags & PINMUX_FLAG_8BIT_MODE) {
+   for (i = start; i <= (start + 3); i++) {
+   s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
+   s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+   s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+   }
+   }
+   for (i = 0; i < 2; i++) {
+   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+   s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+   s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+   }
+   for (i = 3; i <= 6; i++) {
+   s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+   s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+   s5p_gpio_set_drv(bank, i, GPIO_D

Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

Re: [U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

[U-Boot] [PATCH 3/4] EXYNOS: additional Exynos4 SoC series support

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