Re: [U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on imx8m
Hi Troy,
> -Original Message-
> From: Troy Kisky
> Sent: 2019年8月9日 3:52
> To: Peng Fan ; sba...@denx.de; feste...@gmail.com
> Cc: u-boot@lists.denx.de; Jacky Bai ; dl-uboot-imx
>
> Subject: Re: [U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on
> imx8m
>
> On 8/8/2019 2:59 AM, Peng Fan wrote:
> > From: Jacky Bai
> >
> > Refine the ddr init driver to make it more reusable for different DDR
> > type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code.
> >
> > Signed-off-by: Jacky Bai
> > Reviewed-by: Ye Li
> > Signed-off-by: Peng Fan
> > ---
> > drivers/ddr/imx/imx8m/Kconfig| 6 ++
> > drivers/ddr/imx/imx8m/Makefile | 4 +-
> > drivers/ddr/imx/imx8m/ddr4_init.c| 112
> > drivers/ddr/imx/imx8m/ddr_init.c | 168
> ++
> > drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 +
> > drivers/ddr/imx/imx8m/helper.c | 10 +-
> > drivers/ddr/imx/imx8m/lpddr4_init.c | 191
> > ---
> > 7 files changed, 184 insertions(+), 311 deletions(-) delete mode
> > 100644 drivers/ddr/imx/imx8m/ddr4_init.c create mode 100644
> > drivers/ddr/imx/imx8m/ddr_init.c delete mode 100644
> > drivers/ddr/imx/imx8m/lpddr4_init.c
> >
> > diff --git a/drivers/ddr/imx/imx8m/Kconfig
> > b/drivers/ddr/imx/imx8m/Kconfig index a83b0f43d7..5bf61eb258 100644
> > --- a/drivers/ddr/imx/imx8m/Kconfig
> > +++ b/drivers/ddr/imx/imx8m/Kconfig
> > @@ -16,6 +16,12 @@ config IMX8M_DDR4
> > help
> > Select the i.MX8M DDR4 driver support on i.MX8M SOC.
> >
> > +config IMX8M_DDR3L
> > + bool "imx8m ddr3l"
> > + select IMX8M_DRAM
> > + help
> > + Select the i.MX8M DDR3L driver support on i.MX8M SOC.
> > +
> > config SAVED_DRAM_TIMING_BASE
> > hex "Define the base address for saved dram timing"
> > help
> > diff --git a/drivers/ddr/imx/imx8m/Makefile
> > b/drivers/ddr/imx/imx8m/Makefile index 64f9ab20e6..bd9bcb8d53 100644
> > --- a/drivers/ddr/imx/imx8m/Makefile
> > +++ b/drivers/ddr/imx/imx8m/Makefile
> > @@ -5,7 +5,5 @@
> > #
> >
> > ifdef CONFIG_SPL_BUILD
> > -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> > ddrphy_csr.o
> > -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
> > -obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
> > +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> > +ddrphy_csr.o ddr_init.o
> > endif
> > diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c
> > b/drivers/ddr/imx/imx8m/ddr4_init.c
> > deleted file mode 100644
> > index b8aa104536..00
> > --- a/drivers/ddr/imx/imx8m/ddr4_init.c
> > +++ /dev/null
> > @@ -1,112 +0,0 @@
> > -// SPDX-License-Identifier: GPL-2.0+
> > -/*
> > - * Copyright 2018 NXP
> > - */
> > -
> > -#include
> > -#include
> > -#include
> > -#include
> > -#include
> > -#include
> > -
> > -void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) -{
> > - int i = 0;
> > -
> > - for (i = 0; i < num; i++) {
> > - reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
> > - ddrc_cfg++;
> > - }
> > -}
> > -
> > -void ddr_init(struct dram_timing_info *dram_timing) -{
> > - volatile unsigned int tmp_t;
> > - /*
> > -* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
> > -* [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
> > -* [4]src_system_rst_b!
> > -*/
> > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F3F);
> > - /* deassert [4]src_system_rst_b! */
> > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F0F);
> > -
> > - /*
> > -* change the clock source of dram_apb_clk_root
> > -* to source 4 --800MHz/4
> > -*/
> > - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> > -CLK_ROOT_SOURCE_SEL(4) |
> > -CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
> > -
> > - dram_pll_init(MHZ(600));
> > -
> > - reg32_write(0x303A00EC, 0x); /* PGC_CPU_MAPPING */
> > - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
> > -
> > - /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
> > - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F06);
> > -
> > - reg32_write(DDRC_DBG1(0), 0x0001);
> > - reg32_write(DDRC_PWRCTL(0), 0x0001);
> > -
> > - while (0 != (0x7 & reg32_
Re: [U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on imx8m
On 8/8/2019 2:59 AM, Peng Fan wrote:
> From: Jacky Bai
>
> Refine the ddr init driver to make it more reusable for different
> DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
> code.
>
> Signed-off-by: Jacky Bai
> Reviewed-by: Ye Li
> Signed-off-by: Peng Fan
> ---
> drivers/ddr/imx/imx8m/Kconfig| 6 ++
> drivers/ddr/imx/imx8m/Makefile | 4 +-
> drivers/ddr/imx/imx8m/ddr4_init.c| 112
> drivers/ddr/imx/imx8m/ddr_init.c | 168 ++
> drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 +
> drivers/ddr/imx/imx8m/helper.c | 10 +-
> drivers/ddr/imx/imx8m/lpddr4_init.c | 191
> ---
> 7 files changed, 184 insertions(+), 311 deletions(-)
> delete mode 100644 drivers/ddr/imx/imx8m/ddr4_init.c
> create mode 100644 drivers/ddr/imx/imx8m/ddr_init.c
> delete mode 100644 drivers/ddr/imx/imx8m/lpddr4_init.c
>
> diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
> index a83b0f43d7..5bf61eb258 100644
> --- a/drivers/ddr/imx/imx8m/Kconfig
> +++ b/drivers/ddr/imx/imx8m/Kconfig
> @@ -16,6 +16,12 @@ config IMX8M_DDR4
> help
> Select the i.MX8M DDR4 driver support on i.MX8M SOC.
>
> +config IMX8M_DDR3L
> + bool "imx8m ddr3l"
> + select IMX8M_DRAM
> + help
> + Select the i.MX8M DDR3L driver support on i.MX8M SOC.
> +
> config SAVED_DRAM_TIMING_BASE
> hex "Define the base address for saved dram timing"
> help
> diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
> index 64f9ab20e6..bd9bcb8d53 100644
> --- a/drivers/ddr/imx/imx8m/Makefile
> +++ b/drivers/ddr/imx/imx8m/Makefile
> @@ -5,7 +5,5 @@
> #
>
> ifdef CONFIG_SPL_BUILD
> -obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> ddrphy_csr.o
> -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
> -obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
> +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
> ddrphy_csr.o ddr_init.o
> endif
> diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c
> b/drivers/ddr/imx/imx8m/ddr4_init.c
> deleted file mode 100644
> index b8aa104536..00
> --- a/drivers/ddr/imx/imx8m/ddr4_init.c
> +++ /dev/null
> @@ -1,112 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2018 NXP
> - */
> -
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -
> -void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
> -{
> - int i = 0;
> -
> - for (i = 0; i < num; i++) {
> - reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
> - ddrc_cfg++;
> - }
> -}
> -
> -void ddr_init(struct dram_timing_info *dram_timing)
> -{
> - volatile unsigned int tmp_t;
> - /*
> - * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
> - * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
> - * [4]src_system_rst_b!
> - */
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F3F);
> - /* deassert [4]src_system_rst_b! */
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F0F);
> -
> - /*
> - * change the clock source of dram_apb_clk_root
> - * to source 4 --800MHz/4
> - */
> - clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
> - CLK_ROOT_SOURCE_SEL(4) |
> - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
> -
> - dram_pll_init(MHZ(600));
> -
> - reg32_write(0x303A00EC, 0x); /* PGC_CPU_MAPPING */
> - reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
> -
> - /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F06);
> -
> - reg32_write(DDRC_DBG1(0), 0x0001);
> - reg32_write(DDRC_PWRCTL(0), 0x0001);
> -
> - while (0 != (0x7 & reg32_read(DDRC_STAT(0
> - ;
> -
> - /* config the uMCTL2's registers */
> - ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
> -
> - reg32_write(DDRC_RFSHCTL3(0), 0x0001);
> - /* RESET: DEASSERTED */
> - /* RESET: - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F04);
> - reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00);
> -
> - reg32_write(DDRC_DBG1(0), 0x);
> - reg32_write(DDRC_PWRCTL(0), 0x0aa);
> - reg32_write(DDRC_SWCTL(0), 0x);
> -
> - reg32_write(DDRC_DFIMISC(0), 0x);
> -
> - /* config the DDR PHY's registers */
> - ddr_cfg_phy(dram_timing);
> -
> - do {
> - tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
> -4 * 0x00020097);
> - } while (tmp_t != 0);
> -
> - reg32_write(DDRC_DFIMISC(0), 0x0020);
> -
> - /* wait DFISTAT.dfi_init_complete to 1 */
> - while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0
> - ;
> -
> - /* clear DFIMISC.dfi_init_complete_en */
> - reg32_write(DDRC_DFIMISC(0), 0x);
> - /* set DFIMISC.dfi_init_complete_en again */
> - reg32_write(DDRC_DFIMISC(0),
[U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on imx8m
From: Jacky Bai
Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
code.
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx8m/Kconfig| 6 ++
drivers/ddr/imx/imx8m/Makefile | 4 +-
drivers/ddr/imx/imx8m/ddr4_init.c| 112
drivers/ddr/imx/imx8m/ddr_init.c | 168 ++
drivers/ddr/imx/imx8m/ddrphy_utils.c | 4 +
drivers/ddr/imx/imx8m/helper.c | 10 +-
drivers/ddr/imx/imx8m/lpddr4_init.c | 191 ---
7 files changed, 184 insertions(+), 311 deletions(-)
delete mode 100644 drivers/ddr/imx/imx8m/ddr4_init.c
create mode 100644 drivers/ddr/imx/imx8m/ddr_init.c
delete mode 100644 drivers/ddr/imx/imx8m/lpddr4_init.c
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
index a83b0f43d7..5bf61eb258 100644
--- a/drivers/ddr/imx/imx8m/Kconfig
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -16,6 +16,12 @@ config IMX8M_DDR4
help
Select the i.MX8M DDR4 driver support on i.MX8M SOC.
+config IMX8M_DDR3L
+ bool "imx8m ddr3l"
+ select IMX8M_DRAM
+ help
+ Select the i.MX8M DDR3L driver support on i.MX8M SOC.
+
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
index 64f9ab20e6..bd9bcb8d53 100644
--- a/drivers/ddr/imx/imx8m/Makefile
+++ b/drivers/ddr/imx/imx8m/Makefile
@@ -5,7 +5,5 @@
#
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
-obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
-obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
+obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o
ddrphy_csr.o ddr_init.o
endif
diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c
b/drivers/ddr/imx/imx8m/ddr4_init.c
deleted file mode 100644
index b8aa104536..00
--- a/drivers/ddr/imx/imx8m/ddr4_init.c
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
-{
- int i = 0;
-
- for (i = 0; i < num; i++) {
- reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
- ddrc_cfg++;
- }
-}
-
-void ddr_init(struct dram_timing_info *dram_timing)
-{
- volatile unsigned int tmp_t;
- /*
-* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
-* [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
-* [4]src_system_rst_b!
-*/
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F3F);
- /* deassert [4]src_system_rst_b! */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F0F);
-
- /*
-* change the clock source of dram_apb_clk_root
-* to source 4 --800MHz/4
-*/
- clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
-CLK_ROOT_SOURCE_SEL(4) |
-CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
-
- dram_pll_init(MHZ(600));
-
- reg32_write(0x303A00EC, 0x); /* PGC_CPU_MAPPING */
- reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
-
- /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F06);
-
- reg32_write(DDRC_DBG1(0), 0x0001);
- reg32_write(DDRC_PWRCTL(0), 0x0001);
-
- while (0 != (0x7 & reg32_read(DDRC_STAT(0
- ;
-
- /* config the uMCTL2's registers */
- ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
-
- reg32_write(DDRC_RFSHCTL3(0), 0x0001);
- /* RESET: DEASSERTED */
- /* RESET:
+#include
+#include
+#include
+#include
+#include
+
+void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
+{
+ int i = 0;
+
+ for (i = 0; i < num; i++) {
+ reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
+ ddrc_cfg++;
+ }
+}
+
+void ddr_init(struct dram_timing_info *dram_timing)
+{
+ unsigned int tmp, initial_drate, target_freq;
+
+ printf("DDRINFO: start DRAM init\n");
+
+ /* Step1: Follow the power up procedure */
+ if (is_imx8mq()) {
+ reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F0F);
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F0F);
+ reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00);
+ } else {
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F1F);
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F0F);
+ }
+
+ debug("DDRINFO: cfg clk\n");
+ /* change the clock source of dram_apb_clk_root: source 4 800MHz /4 =
200MHz */
+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(4) |
+
