subject:"\[U\-Boot\] \[PATCH 3\/5\] rockchip\: video\: Add mipi dsi driver for rk3399"

Re: [U-Boot] [PATCH 3/5] rockchip: video: Add mipi dsi driver for rk3399

2017-04-11 Thread Simon Glass

Hi Eric,

On 9 April 2017 at 20:41, Eric Gao  wrote:
> Add mipi dsi driver for rk chip, To enable this
> you need to enable DM, DM_VIDEO, DM_ROCKCHIP_VIDEO,
> DISPLAY_MIPI in menuconfig. And enable rk808,and it's
> corresponding i2c.

General comment:

Can you please format your commit message, comments and code to use up
more of the 80 columns?

Git commit messages should be word-wrapped to <=75 columns I think (so
that git log looks right in 80 columns). Comments, etc. should be <=80
cols.

Kconfig also should use more of the width.

Set your editor to show a line at 80cols!
>
> Signed-off-by: Eric Gao 
> ---
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3399.h  |   1 +
>  arch/arm/include/asm/arch-rockchip/grf_rk3399.h  |  25 ++
>  arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 189 +
>  arch/arm/include/asm/arch-rockchip/vop_rk3288.h  |   1 +
>  drivers/video/Kconfig|   2 +
>  drivers/video/rockchip/Kconfig   |  47 +++
>  drivers/video/rockchip/Makefile  |   6 +-
>  drivers/video/rockchip/rk_mipi.c | 465 
> +++
>  drivers/video/rockchip/rk_vop.c  |  39 +-
>  9 files changed, 768 insertions(+), 7 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
>  create mode 100644 drivers/video/rockchip/Kconfig
>  create mode 100644 drivers/video/rockchip/rk_mipi.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h 
> b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> index cf830d0..e9e5810 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
> @@ -70,6 +70,7 @@ struct rk3399_cru {
>  };
>  check_member(rk3399_cru, sdio1_con[1], 0x594);
>  #define MHz100
> +#define MHZ100
>  #define KHz1000
>  #define OSC_HZ (24*MHz)
>  #define APLL_HZ(600*MHz)
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h 
> b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> index 62d8496..2bf58da 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
> @@ -399,6 +399,31 @@ enum {
> GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
> GRF_UART_DBG_SEL_C  = 2,
>
> +   /* GRF_SOC_CON20 */
> +   GRF_DSI0_VOP_SEL_SHIFT  = 0,
> +   GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
> +   GRF_DSI0_VOP_SEL_B  = 0,
> +   GRF_DSI0_VOP_SEL_L,
> +
> +   /* GRF_SOC_CON22 */
> +   GRF_DPHY_TX0_RXMODE_SHIFT = 0,
> +   GRF_DPHY_TX0_RXMODE_MASK =
> +   0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
> +   GRF_DPHY_TX0_RXMODE_EN = 0xb,
> +   GRF_DPHY_TX0_RXMODE_DIS = 0,
> +
> +   GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
> +   GRF_DPHY_TX0_TXSTOPMODE_MASK =
> +   0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
> +   GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
> +   GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
> +
> +   GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
> +   GRF_DPHY_TX0_TURNREQUEST_MASK =
> +   0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
> +   GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
> +   GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
> +
> /*  PMUGRF_GPIO0A_IOMUX */
> PMUGRF_GPIO0A6_SEL_SHIFT= 12,
> PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
> diff --git a/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h 
> b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
> new file mode 100644
> index 000..9a1fffb
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
> @@ -0,0 +1,189 @@
> +/*
> + * Copyright (C) 2017-2025 Fuzhou Rockchip Electronics Co., Ltd
> + * author: eric@rock-chips.com
> + * create date: 2017-03-31
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef RK33_MIPI_DSI_H
> +#define RK33_MIPI_DSI_H
> +
> +/*
> + * All these mipi controller register declaration provide
> + * reg address offset, bits width, bit offset for a
> + * specified register bits. With these message, we can
> + * set or clear every bits individually for a 32bit width
> + * register. We use DSI_HOST_BITS macro definition to
> + * combinat these message using the following format:
> + * val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
> + * for example:
> + * #define SHUTDOWNZ   DSI_HOST_BITS(0X004, 1, 0)
> + * means SHUTDOWNZ is a signal reg bit with bit offset
> + * qual 0,and it's reg addr offset is 0x004.The conbinat
> + * result  = (0x004 << 16) | (1 << 8) | 0

A more conventional idea might be:

struct dsi_host_reg {
  u16 addr;
  u8 bits;
  u8 bit_offset;
};

enum dsi_host_reg_t {
   VERSION,
   SHUTDOWNZ,
   ...
   DSI_HOST_REG_COUNT,
};

#define DSI_HOST_REG(addr, bits, bit_offset) { .addr = _addr; bits =
_bits; bit_offset = _bit_offset }

static const struct dsi_host_reg

[U-Boot] [PATCH 3/5] rockchip: video: Add mipi dsi driver for rk3399

2017-04-09 Thread Eric Gao

Add mipi dsi driver for rk chip, To enable this
you need to enable DM, DM_VIDEO, DM_ROCKCHIP_VIDEO,
DISPLAY_MIPI in menuconfig. And enable rk808,and it's
corresponding i2c.

Signed-off-by: Eric Gao 
---

 arch/arm/include/asm/arch-rockchip/cru_rk3399.h  |   1 +
 arch/arm/include/asm/arch-rockchip/grf_rk3399.h  |  25 ++
 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h | 189 +
 arch/arm/include/asm/arch-rockchip/vop_rk3288.h  |   1 +
 drivers/video/Kconfig|   2 +
 drivers/video/rockchip/Kconfig   |  47 +++
 drivers/video/rockchip/Makefile  |   6 +-
 drivers/video/rockchip/rk_mipi.c | 465 +++
 drivers/video/rockchip/rk_vop.c  |  39 +-
 9 files changed, 768 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
 create mode 100644 drivers/video/rockchip/Kconfig
 create mode 100644 drivers/video/rockchip/rk_mipi.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index cf830d0..e9e5810 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -70,6 +70,7 @@ struct rk3399_cru {
 };
 check_member(rk3399_cru, sdio1_con[1], 0x594);
 #define MHz100
+#define MHZ100
 #define KHz1000
 #define OSC_HZ (24*MHz)
 #define APLL_HZ(600*MHz)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index 62d8496..2bf58da 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -399,6 +399,31 @@ enum {
GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
GRF_UART_DBG_SEL_C  = 2,
 
+   /* GRF_SOC_CON20 */
+   GRF_DSI0_VOP_SEL_SHIFT  = 0,
+   GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+   GRF_DSI0_VOP_SEL_B  = 0,
+   GRF_DSI0_VOP_SEL_L,
+
+   /* GRF_SOC_CON22 */
+   GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+   GRF_DPHY_TX0_RXMODE_MASK =
+   0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+   GRF_DPHY_TX0_RXMODE_EN = 0xb,
+   GRF_DPHY_TX0_RXMODE_DIS = 0,
+
+   GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+   GRF_DPHY_TX0_TXSTOPMODE_MASK =
+   0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+   GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
+   GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
+
+   GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+   GRF_DPHY_TX0_TURNREQUEST_MASK =
+   0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+   GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
+   GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
+
/*  PMUGRF_GPIO0A_IOMUX */
PMUGRF_GPIO0A6_SEL_SHIFT= 12,
PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
diff --git a/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h 
b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
new file mode 100644
index 000..9a1fffb
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/mipi_rk3399.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2017-2025 Fuzhou Rockchip Electronics Co., Ltd
+ * author: eric@rock-chips.com
+ * create date: 2017-03-31
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef RK33_MIPI_DSI_H
+#define RK33_MIPI_DSI_H
+
+/*
+ * All these mipi controller register declaration provide
+ * reg address offset, bits width, bit offset for a
+ * specified register bits. With these message, we can
+ * set or clear every bits individually for a 32bit width
+ * register. We use DSI_HOST_BITS macro definition to
+ * combinat these message using the following format:
+ * val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
+ * for example:
+ * #define SHUTDOWNZ   DSI_HOST_BITS(0X004, 1, 0)
+ * means SHUTDOWNZ is a signal reg bit with bit offset
+ * qual 0,and it's reg addr offset is 0x004.The conbinat
+ * result  = (0x004 << 16) | (1 << 8) | 0
+ */
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
+   ((addr<<16) | (bits<<8) | (bit_offset))
+
+/* DWC_DSI_VERSION_0X3133302A */
+#define VERSIONDSI_HOST_BITS(0X000, 32, 0)
+#define SHUTDOWNZ  DSI_HOST_BITS(0X004, 1, 0)
+#define TO_CLK_DIVISIONDSI_HOST_BITS(0X008, 8, 8)
+#define TX_ESC_CLK_DIVISIONDSI_HOST_BITS(0X008, 8, 0)
+#define DPI_VCID   DSI_HOST_BITS(0X00C, 2, 0)
+#define EN18_LOOSELY   DSI_HOST_BITS(0X010, 1, 8)
+#define DPI_COLOR_CODING   DSI_HOST_BITS(0X010, 4, 0)
+#define COLORM_ACTIVE_LOW  DSI_HOST_BITS(0X014, 1, 4)
+#define SHUTD_ACTIVE_LOW   DSI_HOST_BITS(0X014, 1, 3)
+#define HSYNC_ACTIVE_LOW   DSI_HOST_BITS(0X014, 1, 2)
+#define VSYNC_ACTIVE_LOW   DSI_HOST_BITS(0X014, 1, 1)
+#define DATAEN_ACTIVE_LOW  DSI_HOST_BITS(0X014, 1, 0)
+#define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0X018, 8, 16)
+#define

Re: [U-Boot] [PATCH 3/5] rockchip: video: Add mipi dsi driver for rk3399

[U-Boot] [PATCH 3/5] rockchip: video: Add mipi dsi driver for rk3399

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