Re: [U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31
Hi,
On 09/22/2014 04:07 AM, Chen-Yu Tsai wrote:
Hi,
On Mon, Sep 22, 2014 at 1:05 AM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Oliver Schinagl oli...@schinagl.nl
To setup clocks and control voltages.
perhaps add ... For P2WI and PIO, since that is apparently what it is
doing?
Sounds good. I'll expand the message to mention what the PRCM
controls, and what we actually use.
HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits
I suppose these comments aren't really meaningful in the final commit
message, probably better to drop them.
I was trying to keep the history of the patches intact.
If Hans agress, I can drop them.
Yes dropping them for upstreaming is fine.
Regards,
Hans
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
Typo in Allwiner
+ reg_val = readl(prcm-apb0_gate);
+ reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
+ writel(reg_val, prcm-apb0_gate);
+
+ reg_val = readl(prcm-apb0_reset);
+ reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
+ writel(reg_val, prcm-apb0_reset);
I think these should both use the setbits helper.
Right. Will change them.
Thanks!
ChenYu
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Re: [U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Oliver Schinagl oli...@schinagl.nl
To setup clocks and control voltages.
perhaps add ... For P2WI and PIO, since that is apparently what it is
doing?
HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits
I suppose these comments aren't really meaningful in the final commit
message, probably better to drop them.
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
Typo in Allwiner
+ reg_val = readl(prcm-apb0_gate);
+ reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
+ writel(reg_val, prcm-apb0_gate);
+
+ reg_val = readl(prcm-apb0_reset);
+ reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
+ writel(reg_val, prcm-apb0_reset);
I think these should both use the setbits helper.
Ian.
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Re: [U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31
Hi,
On Mon, Sep 22, 2014 at 1:05 AM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Oliver Schinagl oli...@schinagl.nl
To setup clocks and control voltages.
perhaps add ... For P2WI and PIO, since that is apparently what it is
doing?
Sounds good. I'll expand the message to mention what the PRCM
controls, and what we actually use.
HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits
I suppose these comments aren't really meaningful in the final commit
message, probably better to drop them.
I was trying to keep the history of the patches intact.
If Hans agress, I can drop them.
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
Typo in Allwiner
+ reg_val = readl(prcm-apb0_gate);
+ reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
+ writel(reg_val, prcm-apb0_gate);
+
+ reg_val = readl(prcm-apb0_reset);
+ reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
+ writel(reg_val, prcm-apb0_reset);
I think these should both use the setbits helper.
Right. Will change them.
Thanks!
ChenYu
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[U-Boot] [PATCH 3/7] ARM: sun6i: Add support for the new power control module found on the A31
From: Oliver Schinagl oli...@schinagl.nl
To setup clocks and control voltages.
HdG: Rename the files from the somewhat generic pmu name to prcm.{c,h}
HdG: Make the prcm code only deal with the prcm, remove axp221 bits
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
[w...@csie.org: spacing fixes reported by checkpatch.pl]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/prcm.c| 37 +
arch/arm/include/asm/arch-sunxi/prcm.h | 238 +
3 files changed, 276 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/prcm.c
create mode 100644 arch/arm/include/asm/arch-sunxi/prcm.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index e9721b2..f0473d2 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
+obj-$(CONFIG_SUN6I)+= prcm.o
obj-$(CONFIG_SUN4I)+= clock_sun4i.o
obj-$(CONFIG_SUN5I)+= clock_sun4i.o
obj-$(CONFIG_SUN7I)+= clock_sun4i.o
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c
new file mode 100644
index 000..8f9bea9
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/prcm.c
@@ -0,0 +1,37 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl oli...@schinagl.nl
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * Berg Xing bergx...@allwinnertech.com
+ * Tom Cubie tangli...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/cpu.h
+#include asm/arch/prcm.h
+#include asm/arch/sys_proto.h
+
+void prcm_init_apb0(void)
+{
+ struct sunxi_prcm_reg *prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ u32 reg_val;
+
+ reg_val = readl(prcm-apb0_gate);
+ reg_val |= PRCM_APB0_GATE_P2WI | PRCM_APB0_GATE_PIO;
+ writel(reg_val, prcm-apb0_gate);
+
+ reg_val = readl(prcm-apb0_reset);
+ reg_val |= PRCM_APB0_RESET_P2WI | PRCM_APB0_RESET_PIO;
+ writel(reg_val, prcm-apb0_reset);
+}
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h
b/arch/arm/include/asm/arch-sunxi/prcm.h
new file mode 100644
index 000..1b40f09
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -0,0 +1,238 @@
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl oli...@schinagl.nl
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * Berg Xing bergx...@allwinnertech.com
+ * Tom Cubie tangli...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) 0x3) 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+ __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) 0x1f) 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+ __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) 0x3) 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+ __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) 0x3) 0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+ __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 0)
+#define PRCM_APB0_GATE_IR (0x1 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 2)
+#define PRCM_APB0_GATE_P2WI (0x1 3)
+#define PRCM_APB0_GATE_UART (0x1 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 5)
+#define PRCM_APB0_GATE_I2C (0x1 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 0)
+#define PRCM_APB0_RESET_IR (0x1 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 2)
+#define PRCM_APB0_RESET_P2WI (0x1 3)
+#define PRCM_APB0_RESET_UART (0x1 4)
+#define
