Re: [U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include
On Mon, Oct 7, 2019 at 3:38 PM Dalon L Westergreen
wrote:
>
> On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
>
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
> >
>
>
> Add a common u-boot devicetree include file for the SocFPGA
>
> Arria10 device.
>
>
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basically
>
> the same thing, except more fine-grained ?
>
>
> I wanted to keep the dts fragment dependent on the handoff header separate
> from the
> generic base u-boot include.
Hmm, ok, I see. Is it encouraged to add more header files in arch/arm/dts?
If so, I wouldn't be too opposed on going that way for gen5 as well...
Regards,
Simon
>
>
> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>
> new file mode 100644
>
> index 00..bd4f1271f3
>
> --- /dev/null
>
> +++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>
> @@ -0,0 +1,206 @@
>
> +// SPDX-License-Identifier: GPL-2.0
>
> +/*
>
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
>
> + */
>
> +
>
> +/ {
>
> + #address-cells = <1>;
>
> + #size-cells = <1>;
>
> +
>
> + chosen {
>
> + tick-timer =
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + memory@0 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + soc {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + clkmgr@ffd04000 {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + clocks {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + cb_intosc_hs_div2_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + cb_intosc_ls_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + f2s_free_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + osc1 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_pll@40 {
>
> + u-boot,dm-pre-reloc;
>
> +
>
> + main_mpu_base_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_noc_base_clk {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
> +
>
> + main_emaca_clk@68 {
>
> + u-boot,dm-pre-reloc;
>
> + };
>
>
> Do we really need all this in SPL for every board ?
___
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Re: [U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include
On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thing, except more fine-grained ?
I wanted to keep the dts fragment dependent on the handoff header separate from
thegeneric base u-boot include.
> > diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
> > 00..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
> > common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
> > * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+
> > #address-cells = <1>;+ #size-cells = <1>;++chosen {+
> > tick
> > -timer = + u-boot,dm-pre-reloc;+ };++memory@0 {+
> > u-boot,dm-pre-reloc;+ };++soc {+ u-boot,dm-pre-
> > reloc;++clkmgr@ffd04000 {+ u-boot,dm-pre-
> > reloc;++clocks {+
> > u-
> > boot,dm-pre-reloc;++cb_intosc_hs_div
> > 2_clk {+u-boot,dm-pre-reloc;+
> > };++cb_i
> > ntosc_ls_clk {+ u-boot,dm-pre-
> > reloc;+ };++
> > f2s_free_clk {+ u-boot,dm-
> > pre-reloc;+ };++
> > osc1 {+ u-boot,dm-pre-
> > reloc;+ };++
> > main_pll@40 {+ u-boot,dm-
> > pre-reloc;++main_mpu_base_cl
> > k {+u-boot,dm-pre-
> > reloc;+ };++
> > main_noc_base_clk {+
> > u-boot,dm-pre-reloc;+
> > };++main_emaca_clk@68 {+
> > u-boot,dm-pre-reloc;+
> > };
>
> Do we really need all this in SPL for every board ?
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Re: [U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include
On 10/6/19 1:25 AM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>> From: Dalon Westergreen
>>> Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>>
>> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe
>> same
>> thing, except more fine-grained ?
>>> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
>>> b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
>>> 00..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
>>> common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
>>> * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+
>>> #address-cells = <1>;+ #size-cells = <1>;++chosen {+
>>> tick
>>> -timer = + u-boot,dm-pre-reloc;+ };++memory@0 {+
>>> u-boot,dm-pre-reloc;+ };++soc {+ u-boot,dm-pre-
>>> reloc;++clkmgr@ffd04000 {+ u-boot,dm-pre-
>>> reloc;++clocks {+
>>> u-
>>> boot,dm-pre-reloc;++cb_intosc_hs_div
>>> 2_clk {+u-boot,dm-pre-reloc;+
>>> };++cb_i
>>> ntosc_ls_clk {+ u-boot,dm-pre-
>>> reloc;+ };++
>>> f2s_free_clk {+ u-boot,dm-
>>> pre-reloc;+ };++
>>> osc1 {+ u-boot,dm-pre-
>>> reloc;+ };++
>>> main_pll@40 {+ u-boot,dm-
>>> pre-reloc;++main_mpu_base_cl
>>> k {+u-boot,dm-pre-
>>> reloc;+ };++
>>> main_noc_base_clk {+
>>> u-boot,dm-pre-reloc;+
>>> };++main_emaca_clk@68 {+
>>> u-boot,dm-pre-reloc;+
>>> };
>>
>> Do we really need all this in SPL for every board ?
>
> We likely don't, but we arent that memory constrained in a10 and this
> simplifies
> devicetree creation for custom boards.
We shouldn't enable what we don't need in SPL.
> We do have customers using ethernet
> in spl, for example. I can slim this down, but is it necessary?
Just enable the necessary clock in the board-specific DT, since it's a
board-specific configuration.
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Re: [U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include
On Sat, 2019-10-05 at 01:49 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen
> > Add a common u-boot devicetree include file for the SocFPGAArria10 device.
>
> Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basicallythe same
> thing, except more fine-grained ?
> > diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsinew file mode 100644index
> > 00..bd4f1271f3--- /dev/null+++ b/arch/arm/dts/socfpga_arria10-
> > common-u-boot.dtsi@@ -0,0 +1,206 @@+// SPDX-License-Identifier: GPL-2.0+/*+
> > * Copyright Altera Corporation (C) 2014. All rights reserved.+ */++/ {+
> > #address-cells = <1>;+ #size-cells = <1>;++chosen {+
> > tick
> > -timer = + u-boot,dm-pre-reloc;+ };++memory@0 {+
> > u-boot,dm-pre-reloc;+ };++soc {+ u-boot,dm-pre-
> > reloc;++clkmgr@ffd04000 {+ u-boot,dm-pre-
> > reloc;++clocks {+
> > u-
> > boot,dm-pre-reloc;++cb_intosc_hs_div
> > 2_clk {+u-boot,dm-pre-reloc;+
> > };++cb_i
> > ntosc_ls_clk {+ u-boot,dm-pre-
> > reloc;+ };++
> > f2s_free_clk {+ u-boot,dm-
> > pre-reloc;+ };++
> > osc1 {+ u-boot,dm-pre-
> > reloc;+ };++
> > main_pll@40 {+ u-boot,dm-
> > pre-reloc;++main_mpu_base_cl
> > k {+u-boot,dm-pre-
> > reloc;+ };++
> > main_noc_base_clk {+
> > u-boot,dm-pre-reloc;+
> > };++main_emaca_clk@68 {+
> > u-boot,dm-pre-reloc;+
> > };
>
> Do we really need all this in SPL for every board ?
We likely don't, but we arent that memory constrained in a10 and this simplifies
devicetree creation for custom boards. We do have customers using ethernet
in spl, for example. I can slim this down, but is it necessary?
--dalon
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Re: [U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include
On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen
>
> Add a common u-boot devicetree include file for the SocFPGA
> Arria10 device.
Isn't arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi doing basically
the same thing, except more fine-grained ?
> diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> new file mode 100644
> index 00..bd4f1271f3
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
> @@ -0,0 +1,206 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright Altera Corporation (C) 2014. All rights reserved.
> + */
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen {
> + tick-timer =
> + u-boot,dm-pre-reloc;
> + };
> +
> + memory@0 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + soc {
> + u-boot,dm-pre-reloc;
> +
> + clkmgr@ffd04000 {
> + u-boot,dm-pre-reloc;
> +
> + clocks {
> + u-boot,dm-pre-reloc;
> +
> + cb_intosc_hs_div2_clk {
> + u-boot,dm-pre-reloc;
> + };
> +
> + cb_intosc_ls_clk {
> + u-boot,dm-pre-reloc;
> + };
> +
> + f2s_free_clk {
> + u-boot,dm-pre-reloc;
> + };
> +
> + osc1 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + main_pll@40 {
> + u-boot,dm-pre-reloc;
> +
> + main_mpu_base_clk {
> + u-boot,dm-pre-reloc;
> + };
> +
> + main_noc_base_clk {
> + u-boot,dm-pre-reloc;
> + };
> +
> + main_emaca_clk@68 {
> + u-boot,dm-pre-reloc;
> + };
Do we really need all this in SPL for every board ?
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[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include
From: Dalon Westergreen
Add a common u-boot devicetree include file for the SocFPGA
Arria10 device.
Signed-off-by: Dalon Westergreen
---
.../dts/socfpga_arria10-common-u-boot.dtsi| 206 ++
1 file changed, 206 insertions(+)
create mode 100644 arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
new file mode 100644
index 00..bd4f1271f3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ tick-timer =
+ u-boot,dm-pre-reloc;
+ };
+
+ memory@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ clkmgr@ffd04000 {
+ u-boot,dm-pre-reloc;
+
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ cb_intosc_hs_div2_clk {
+ u-boot,dm-pre-reloc;
+ };
+
+ cb_intosc_ls_clk {
+ u-boot,dm-pre-reloc;
+ };
+
+ f2s_free_clk {
+ u-boot,dm-pre-reloc;
+ };
+
+ osc1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_pll@40 {
+ u-boot,dm-pre-reloc;
+
+ main_mpu_base_clk {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_noc_base_clk {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_emaca_clk@68 {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_emacb_clk@6c {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_emac_ptp_clk@70 {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_gpio_db_clk@74 {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_sdmmc_clk@78 {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_s2f_usr0_clk@7c {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_s2f_usr1_clk@80 {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_hmc_pll_ref_clk@84 {
+ u-boot,dm-pre-reloc;
+ };
+
+ main_periph_ref_clk@9c {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ periph_pll@c0 {
+ u-boot,dm-pre-reloc;
+
+ peri_mpu_base_clk {
+ u-boot,dm-pre-reloc;
+ };
+
+ peri_noc_base_clk {
+ u-boot,dm-pre-reloc;
+ };
+
+ peri_emaca_clk@e8 {
+ u-boot,dm-pre-reloc;
+ };
+
+ peri_emacb_clk@ec {
+
