[U-Boot] [PATCH 4/4] ARM: mx6: ddr: Add support for iMX6SX

[sbabic]

> This patch adds support for iMX6SX MMDC into the DDR calibration
> code. The only difference between MX6DQ and MX6SX is that the SX
> has 2 SDQS registers, while the DQ has 8.
> Signed-off-by: Marek Vasut 
> Cc: Eric Nelson 
> Cc: Fabio Estevam 
> Cc: Stefano Babic 
> Reviewed-by: Eric Nelson 
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 4/4] ARM: mx6: ddr: Add support for iMX6SX

[Eric Nelson]

Hi Marek,

On 11/26/19 1:34 AM, Marek Vasut wrote:

This patch adds support for iMX6SX MMDC into the DDR calibration
code. The only difference between MX6DQ and MX6SX is that the SX
has 2 SDQS registers, while the DQ has 8.

Signed-off-by: Marek Vasut 
Cc: Eric Nelson 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
  arch/arm/mach-imx/mx6/ddr.c | 18 ++
  1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index b2402f75db..8ed8b79c8b 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -247,12 +247,22 @@ int mmdc_do_write_level_calibration(struct 
mx6_ddr_sysinfo const *sysinfo)
  
  static void mmdc_set_sdqs(bool set)

  {
-   struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
+   struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
-   u32 sdqs = (u32)(_ddr_iomux->dram_sdqs0);
-   int i;
+   struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
+   (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+   int i, sdqs_cnt;
+   u32 sdqs;
+
+   if (is_mx6sx()) {
+   sdqs = (u32)(_ddr_iomux->dram_sdqs0);
+   sdqs_cnt = 2;
+   } else {/* MX6DQ */
+   sdqs = (u32)(_ddr_iomux->dram_sdqs0);
+   sdqs_cnt = 8;
+   }
  
-	for (i = 0; i < 8; i++) {

+   for (i = 0; i < sdqs_cnt; i++) {
if (set)
setbits_le32(sdqs + (4 * i), 0x7000);
else



Reviewed-by: Eric Nelson 
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[U-Boot] [PATCH 4/4] ARM: mx6: ddr: Add support for iMX6SX

[Marek Vasut]

This patch adds support for iMX6SX MMDC into the DDR calibration
code. The only difference between MX6DQ and MX6SX is that the SX
has 2 SDQS registers, while the DQ has 8.

Signed-off-by: Marek Vasut 
Cc: Eric Nelson 
Cc: Fabio Estevam 
Cc: Stefano Babic 
---
 arch/arm/mach-imx/mx6/ddr.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index b2402f75db..8ed8b79c8b 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -247,12 +247,22 @@ int mmdc_do_write_level_calibration(struct 
mx6_ddr_sysinfo const *sysinfo)
 
 static void mmdc_set_sdqs(bool set)
 {
-   struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
+   struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
-   u32 sdqs = (u32)(_ddr_iomux->dram_sdqs0);
-   int i;
+   struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
+   (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+   int i, sdqs_cnt;
+   u32 sdqs;
+
+   if (is_mx6sx()) {
+   sdqs = (u32)(_ddr_iomux->dram_sdqs0);
+   sdqs_cnt = 2;
+   } else {/* MX6DQ */
+   sdqs = (u32)(_ddr_iomux->dram_sdqs0);
+   sdqs_cnt = 8;
+   }
 
-   for (i = 0; i < 8; i++) {
+   for (i = 0; i < sdqs_cnt; i++) {
if (set)
setbits_le32(sdqs + (4 * i), 0x7000);
else
-- 
2.24.0

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