Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Mon, 2019-10-07 at 16:45 +0200, Simon Goldschmidt wrote:
> There's something wrong with your mailer: indentation of replies doesn't
> seemto work. It gets kind of hard to read who wrote what...
> On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen<
> dalon.westergr...@linux.intel.com> wrote:
> > On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> > Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen <
> > dalon.westergr...@intel.com
> > 
> > 
> >   > dalon.westergr...@intel.com
> > 
> > 
> > Generic handoff devicetree include uses a header generated bythe qts-filter-
> > a10.sh script in mach-socfpga.  The scriptcreates the header based on design
> > specific implementationsfor clock and pinmux configurations.
> > 
> > [...]
> > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > 
> > [...]
> > - clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+ compatible =
> > "altr,socfpga-a10-clk-init";+ reg = <0xffd04000 0x0200>;+
> > reg-names = "soc_clock_manager_OCP_SLV"; u-boot,dm-pre-
> > reloc;   mainpll {+ vco0-psrc =
> > ;+ vco1-denom =
> > ;+ vco1-numer =
> > ;
> > 
> > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the board
> > specific header.  The format
> > and #define names are in fact common.
> > 
> > OK, I now see what you're doing here. Can you explain that in a bit more
> > detail in the commit message ?
> > 
> > Basically socfpga_board.h is included socfpga_board.dts , and then the
> > preprocessor correctly expands the values from socfpga_board.h in the
> > socfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks in
> > the u-boot.dtsi
> > 
> > I'm (still) working on a series to bring gen5 completely to devicetree,
> > so that the 'qts' directories can be removed. I chose a different
> > approach however, in that I generated everything into a '-handoff.dtsi'
> > file (*). I'd be happy if we could find a common mechanism for all
> > socfpga sub-archs. How does S10/Agilex handle this?
> > 
> > (*): Gen5 has the downside that we're low on memory in SPL (regarding
> > DM), and as we require large binary arrays there, I chose to encode the
> > binary blob arrays in host byte order so that they could be used
> > in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe
> > that doesn't fit A10/S10/Agilex anyway?
> > 
> > Can you share your patch set with me, privately or otherwise, just so we can
> > take a similarapproach in the devicetree?
> 
> Give me a week max. and I'll send the series as RFC.
> > Also, have you looked at the bsp-editor python source that generates the
> > "generated" filesfrom the bsp-editor?
> > 19.1std/647/linux64/ip/altera/preloader/scripts
> 
> No, I mainly focused on the U-Boot part for now. I just wrote a C programthat
> did the conversion from 'official generated' files to DTS...
> > I am hoping to replace these with a script included in the u-boot source.
> > iocsr.py doesa bunch of binary parsing.
> 
> Right, a direct conversion from compilation output to U-Boot would be
> better.However, that would require Intel to keep that output consistent!
It should be consistent at this point.  i would not worry about that.
> Regards,Simon
> > --dalon
> > 
> > Regards,
> > Simon
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Simon Goldschmidt]

There's something wrong with your mailer: indentation of replies doesn't seem
to work. It gets kind of hard to read who wrote what...

On Mon, Oct 7, 2019 at 4:34 PM Dalon L Westergreen
 wrote:
>
> On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
>
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
>
> On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
>
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
>
> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>
> From: Dalon Westergreen <
>
> dalon.westergr...@intel.com
>
>
>  
> dalon.westergr...@intel.com
>
> >
>
>
> Generic handoff devicetree include uses a header generated bythe qts-filter-
>
> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>
> specific implementationsfor clock and pinmux configurations.
>
>
> [...]
>
> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>
> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>
>
> [...]
>
> - clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+ compatible =
>
> "altr,socfpga-a10-clk-init";+ reg = <0xffd04000 0x0200>;+
>
> reg-names = "soc_clock_manager_OCP_SLV"; u-boot,dm-pre-
>
> reloc;   mainpll {+ vco0-psrc =
>
> ;+ vco1-denom =
>
> ;+ vco1-numer =
>
> ;
>
>
> But these bits are board-specific , they shouldn't be in common DT.
>
>
> This common dtsi requires that the top level u-boot.dtsi include the board
>
> specific header.  The format
>
> and #define names are in fact common.
>
>
> OK, I now see what you're doing here. Can you explain that in a bit more
>
> detail in the commit message ?
>
>
> Basically socfpga_board.h is included socfpga_board.dts , and then the
>
> preprocessor correctly expands the values from socfpga_board.h in the
>
> socfpga_board.dts , so this works for multiple boards too ?
>
>
> Exactly. Will add more detail in the commit message, and slim down the
>
> included clocks in
>
> the u-boot.dtsi
>
>
> I'm (still) working on a series to bring gen5 completely to devicetree,
>
> so that the 'qts' directories can be removed. I chose a different
>
> approach however, in that I generated everything into a '-handoff.dtsi'
>
> file (*). I'd be happy if we could find a common mechanism for all
>
> socfpga sub-archs. How does S10/Agilex handle this?
>
>
> (*): Gen5 has the downside that we're low on memory in SPL (regarding
>
> DM), and as we require large binary arrays there, I chose to encode the
>
> binary blob arrays in host byte order so that they could be used
>
> in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe
>
> that doesn't fit A10/S10/Agilex anyway?
>
>
> Can you share your patch set with me, privately or otherwise, just so we can 
> take a similar
> approach in the devicetree?

Give me a week max. and I'll send the series as RFC.

>
> Also, have you looked at the bsp-editor python source that generates the 
> "generated" files
> from the bsp-editor?
>
> 19.1std/647/linux64/ip/altera/preloader/scripts

No, I mainly focused on the U-Boot part for now. I just wrote a C program
that did the conversion from 'official generated' files to DTS...

>
> I am hoping to replace these with a script included in the u-boot source. 
> iocsr.py does
> a bunch of binary parsing.

Right, a direct conversion from compilation output to U-Boot would be better.
However, that would require Intel to keep that output consistent!

Regards,
Simon

>
> --dalon
>
>
> Regards,
>
> Simon
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > > From: Dalon Westergreen  > > > > >  
> > > > > > Generic handoff devicetree include uses a header generated bythe
> > > > > > qts-filter-a10.sh script in mach-socfpga.  The scriptcreates the
> > > > > > header based on designspecific implementationsfor clock and pinmux
> > > > > > configurations.
> > > > > 
> > > > > [...]
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > > > 
> > > > > [...]
> > > > > > -   clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+
> > > > > > comp
> > > > > > atible ="altr,socfpga-a10-clk-init";+   reg =
> > > > > > <0xffd04000 0x0200>;+   reg-names =
> > > > > > "soc_clock_manager_OCP_SLV";u-boot,dm-pre-reloc;
> > > > > > mainpll {+  vco0-psrc 
> > > > > > =;+ 
> > > > > > vco1-denom =;+   
> > > > > > vco1-numer =;
> > > > > 
> > > > > But these bits are board-specific , they shouldn't be in common DT.
> > > > 
> > > > This common dtsi requires that the top level u-boot.dtsi include the
> > > > boardspecific header.  The formatand #define names are in fact common.
> > > 
> > > OK, I now see what you're doing here. Can you explain that in a bit
> > > moredetail in the commit message ?
> > > Basically socfpga_board.h is included socfpga_board.dts , and then
> > > thepreprocessor correctly expands the values from socfpga_board.h in
> > > thesocfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks inthe u-boot.dtsi
> 
> I'm (still) working on a series to bring gen5 completely to devicetree, so
> that the 'qts' directories can be removed. I chose a different approach
> however, in that I generated everything into a '-handoff.dtsi' file (*). I'd
> be happy if we could find a common mechanism for all socfpga sub-archs. How
> does S10/Agilex handle this?
> (*): Gen5 has the downside that we're low on memory in SPL (regarding DM), and
> as we require large binary arrays there, I chose to encode the binary blob
> arrays in host byte order so that they could be used in-place instead of
> copying them from BE (dtb) to LE (stack/heap). Maybe that doesn't fit
> A10/S10/Agilex anyway?

Can you share your patch set with me, privately or otherwise, just so we can
take a similarapproach in the devicetree?
Also, have you looked at the bsp-editor python source that generates the
"generated" filesfrom the bsp-editor?  
19.1std/647/linux64/ip/altera/preloader/scripts
I am hoping to replace these with a script included in the u-boot
source.  iocsr.py doesa bunch of binary parsing.
--dalon
> Regards,Simon
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen Generic handoff
> > > > devicetree include uses a header generated bythe qts-filter-a10.sh
> > > > script in mach-socfpga.  The scriptcreates the header based on
> > > > designspecific implementationsfor clock and pinmux configurations.
> > > 
> > > [...]
> > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > 
> > > [...]
> > > > -   clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+
> > > > compatible ="altr,socfpga-a10-clk-init";+   reg =
> > > > <0xffd04000 0x0200>;+   reg-names =
> > > > "soc_clock_manager_OCP_SLV";u-boot,dm-pre-reloc;
> > > > mainpll {+  vco0-psrc =;+ 
> > > > 
> > > > vco1-denom =;+   vco1-
> > > > numer =;
> > > 
> > > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the
> > boardspecific header.  The formatand #define names are in fact common.
> 
> OK, I now see what you're doing here. Can you explain that in a bit moredetail
> in the commit message ?
> Basically socfpga_board.h is included socfpga_board.dts , and then
> thepreprocessor correctly expands the values from socfpga_board.h in
> thesocfpga_board.dts , so this works for multiple boards too ?

oh, and yes, it does work for multiple boards, i have already tested this.

--dalon
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 20:05 +0200, Simon Goldschmidt wrote:
> Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:
> > On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> > > On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > > > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > > > From: Dalon Westergreen  > > > > >  
> > > > > > Generic handoff devicetree include uses a header generated bythe
> > > > > > qts-filter-a10.sh script in mach-socfpga.  The scriptcreates the
> > > > > > header based on designspecific implementationsfor clock and pinmux
> > > > > > configurations.
> > > > > 
> > > > > [...]
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > > > 
> > > > > [...]
> > > > > > -   clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+
> > > > > > comp
> > > > > > atible ="altr,socfpga-a10-clk-init";+   reg =
> > > > > > <0xffd04000 0x0200>;+   reg-names =
> > > > > > "soc_clock_manager_OCP_SLV";u-boot,dm-pre-reloc;
> > > > > > mainpll {+  vco0-psrc 
> > > > > > =;+ 
> > > > > > vco1-denom =;+   
> > > > > > vco1-numer =;
> > > > > 
> > > > > But these bits are board-specific , they shouldn't be in common DT.
> > > > 
> > > > This common dtsi requires that the top level u-boot.dtsi include the
> > > > boardspecific header.  The formatand #define names are in fact common.
> > > 
> > > OK, I now see what you're doing here. Can you explain that in a bit
> > > moredetail in the commit message ?
> > > Basically socfpga_board.h is included socfpga_board.dts , and then
> > > thepreprocessor correctly expands the values from socfpga_board.h in
> > > thesocfpga_board.dts , so this works for multiple boards too ?
> > 
> > Exactly. Will add more detail in the commit message, and slim down the
> > included clocks inthe u-boot.dtsi
> 
> I'm (still) working on a series to bring gen5 completely to devicetree, so
> that the 'qts' directories can be removed. I chose a different approach
> however, in that I generated everything into a '-handoff.dtsi' file (*). I'd
> be happy if we could find a common mechanism for all socfpga sub-archs. How
> does S10/Agilex handle this?
> (*): Gen5 has the downside that we're low on memory in SPL (regarding DM), and
> as we require large binary arrays there, I chose to encode the binary blob
> arrays in host byte order so that they could be used in-place instead of
> copying them from BE (dtb) to LE (stack/heap). Maybe that doesn't fit
> A10/S10/Agilex anyway?

S10/Agilex are entirely different.  The onchip ram is loaded with any
configuration data bythe secure device manager.  There is no need to modify the
dts for any io/pll/bridgeconfiguration. 
A10 is better than cv/av in that is requires far less configuration data, and no
dataregarding the dram is needed.  Also, there is no binary parsing required for
extractingthe required data, hence the simple qts-filter-a10.sh.  
I think a -handoff.dtsi is a good approach, but why not do the same thing i do
here anduse a header file for the config data.  that way the -handoff.dtsi can
be common and theheader only needs to be included in the toplevel -u-boot.dtsi?
--dalon
> Regards,Simon
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Simon Goldschmidt]

Am 06.10.2019 um 19:44 schrieb Dalon L Westergreen:

On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:

On 10/6/19 1:19 AM, Dalon L Westergreen wrote:

On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:

On 10/5/19 12:30 AM, Dalon Westergreen wrote:

From: Dalon Westergreen <
dalon.westergr...@intel.com
 
>
Generic handoff devicetree include uses a header generated bythe qts-filter-
a10.sh script in mach-socfpga.  The scriptcreates the header based on design
specific implementationsfor clock and pinmux configurations.


[...]

diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi


[...]

-   clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+
compatible =
"altr,socfpga-a10-clk-init";+ reg = <0xffd04000 0x0200>;+   
reg-names = "soc_clock_manager_OCP_SLV";  u-boot,dm-pre-
reloc;  mainpll {+  vco0-psrc =
;+  vco1-denom =
;+ vco1-numer =
;


But these bits are board-specific , they shouldn't be in common DT.


This common dtsi requires that the top level u-boot.dtsi include the board
specific header.  The format
and #define names are in fact common.


OK, I now see what you're doing here. Can you explain that in a bit more
detail in the commit message ?

Basically socfpga_board.h is included socfpga_board.dts , and then the
preprocessor correctly expands the values from socfpga_board.h in the
socfpga_board.dts , so this works for multiple boards too ?


Exactly. Will add more detail in the commit message, and slim down the 
included clocks in

the u-boot.dtsi


I'm (still) working on a series to bring gen5 completely to devicetree, 
so that the 'qts' directories can be removed. I chose a different 
approach however, in that I generated everything into a '-handoff.dtsi' 
file (*). I'd be happy if we could find a common mechanism for all 
socfpga sub-archs. How does S10/Agilex handle this?


(*): Gen5 has the downside that we're low on memory in SPL (regarding 
DM), and as we require large binary arrays there, I chose to encode the 
binary blob arrays in host byte order so that they could be used 
in-place instead of copying them from BE (dtb) to LE (stack/heap). Maybe 
that doesn't fit A10/S10/Agilex anyway?


Regards,
Simon
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sun, 2019-10-06 at 15:44 +0200, Marek Vasut wrote:
> On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> > On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> > > On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > > > From: Dalon Westergreen Generic handoff
> > > > devicetree include uses a header generated bythe qts-filter-a10.sh
> > > > script in mach-socfpga.  The scriptcreates the header based on
> > > > designspecific implementationsfor clock and pinmux configurations.
> > > 
> > > [...]
> > > > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-
> > > > boot.dtsib/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > > 
> > > [...]
> > > > -   clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+
> > > > compatible ="altr,socfpga-a10-clk-init";+   reg =
> > > > <0xffd04000 0x0200>;+   reg-names =
> > > > "soc_clock_manager_OCP_SLV";u-boot,dm-pre-reloc;
> > > > mainpll {+  vco0-psrc =;+ 
> > > > 
> > > > vco1-denom =;+   vco1-
> > > > numer =;
> > > 
> > > But these bits are board-specific , they shouldn't be in common DT.
> > 
> > This common dtsi requires that the top level u-boot.dtsi include the
> > boardspecific header.  The formatand #define names are in fact common.
> 
> OK, I now see what you're doing here. Can you explain that in a bit moredetail
> in the commit message ?
> Basically socfpga_board.h is included socfpga_board.dts , and then
> thepreprocessor correctly expands the values from socfpga_board.h in
> thesocfpga_board.dts , so this works for multiple boards too ?

Exactly.  Will add more detail in the commit message, and slim down the included
clocks in
the u-boot.dtsi
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Marek Vasut]

On 10/6/19 1:19 AM, Dalon L Westergreen wrote:
> On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
>> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
>>> From: Dalon Westergreen 
>>> Generic handoff devicetree include uses a header generated bythe qts-filter-
>>> a10.sh script in mach-socfpga.  The scriptcreates the header based on design
>>> specific implementationsfor clock and pinmux configurations.
>>
>> [...]
>>> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
>>
>> [...]
>>> -   clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+
>>> compatible =
>>> "altr,socfpga-a10-clk-init";+   reg = <0xffd04000 0x0200>;+ 
>>> reg-names = "soc_clock_manager_OCP_SLV";u-boot,dm-pre-
>>> reloc;  mainpll {+  vco0-psrc =
>>> ;+vco1-denom =
>>> ;+   vco1-numer =
>>> ;
>>
>> But these bits are board-specific , they shouldn't be in common DT.
> 
> This common dtsi requires that the top level u-boot.dtsi include the board
> specific header.  The format
> and #define names are in fact common.

OK, I now see what you're doing here. Can you explain that in a bit more
detail in the commit message ?

Basically socfpga_board.h is included socfpga_board.dts , and then the
preprocessor correctly expands the values from socfpga_board.h in the
socfpga_board.dts , so this works for multiple boards too ?
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon L Westergreen]

On Sat, 2019-10-05 at 01:51 +0200, Marek Vasut wrote:
> On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> > From: Dalon Westergreen 
> > Generic handoff devicetree include uses a header generated bythe qts-filter-
> > a10.sh script in mach-socfpga.  The scriptcreates the header based on design
> > specific implementationsfor clock and pinmux configurations.
> 
> [...]
> > diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> > b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
> 
> [...]
> > -   clock_manager@0xffd04000 {+ clkmgr@0xffd04000 {+
> > compatible =
> > "altr,socfpga-a10-clk-init";+   reg = <0xffd04000 0x0200>;+ 
> > reg-names = "soc_clock_manager_OCP_SLV";u-boot,dm-pre-
> > reloc;  mainpll {+  vco0-psrc =
> > ;+vco1-denom =
> > ;+   vco1-numer =
> > ;
> 
> But these bits are board-specific , they shouldn't be in common DT.

This common dtsi requires that the top level u-boot.dtsi include the board
specific header.  The format
and #define names are in fact common.

--dalon
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Re: [U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Marek Vasut]

On 10/5/19 12:30 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen 
> 
> Generic handoff devicetree include uses a header generated by
> the qts-filter-a10.sh script in mach-socfpga.  The script
> creates the header based on design specific implementations
> for clock and pinmux configurations.

[...]

> diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi 
> b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi

[...]

> - clock_manager@0xffd04000 {
> + clkmgr@0xffd04000 {
> + compatible = "altr,socfpga-a10-clk-init";
> + reg = <0xffd04000 0x0200>;
> + reg-names = "soc_clock_manager_OCP_SLV";
>   u-boot,dm-pre-reloc;
>  
>   mainpll {
> + vco0-psrc = ;
> + vco1-denom = ;
> + vco1-numer = ;

But these bits are board-specific , they shouldn't be in common DT.
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[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon Westergreen]

From: Dalon Westergreen 

Generic handoff devicetree include uses a header generated by
the qts-filter-a10.sh script in mach-socfpga.  The script
creates the header based on design specific implementations
for clock and pinmux configurations.

Signed-off-by: Dalon Westergreen 
---
 .../dts/socfpga_arria10_handoff_u-boot.dtsi   | 232 --
 1 file changed, 216 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
index ef215230c2..69854352a0 100644
--- a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -1,91 +1,291 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 
 / {
-   chosen {
-   u-boot,dm-pre-reloc;
-   };
-
clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
u-boot,dm-pre-reloc;
 
-   altera_arria10_hps_eosc1 {
+   altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = ;
+   clock-output-names = "altera_arria10_hps_eosc1-clk";
u-boot,dm-pre-reloc;
};
 
-   altera_arria10_hps_cb_intosc_ls {
+   altera_arria10_hps_cb_intosc_ls: 
altera_arria10_hps_cb_intosc_ls {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = ;
+   clock-output-names = 
"altera_arria10_hps_cb_intosc_ls-clk";
u-boot,dm-pre-reloc;
};
 
-   altera_arria10_hps_f2h_free {
+   /* Clock source: altera_arria10_hps_f2h_free */
+   altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = ;
+   clock-output-names = "altera_arria10_hps_f2h_free-clk";
u-boot,dm-pre-reloc;
};
};
 
-   clock_manager@0xffd04000 {
+   clkmgr@0xffd04000 {
+   compatible = "altr,socfpga-a10-clk-init";
+   reg = <0xffd04000 0x0200>;
+   reg-names = "soc_clock_manager_OCP_SLV";
u-boot,dm-pre-reloc;
 
mainpll {
+   vco0-psrc = ;
+   vco1-denom = ;
+   vco1-numer = ;
+   mpuclk-cnt = ;
+   mpuclk-src = ;
+   nocclk-cnt = ;
+   nocclk-src = ;
+   cntr2clk-cnt = ;
+   cntr3clk-cnt = ;
+   cntr4clk-cnt = ;
+   cntr5clk-cnt = ;
+   cntr6clk-cnt = ;
+   cntr7clk-cnt = ;
+   cntr7clk-src = ;
+   cntr8clk-cnt = ;
+   cntr9clk-cnt = ;
+   cntr9clk-src = ;
+   cntr15clk-cnt = ;
+   nocdiv-l4mainclk = ;
+   nocdiv-l4mpclk = ;
+   nocdiv-l4spclk = ;
+   nocdiv-csatclk = ;
+   nocdiv-cstraceclk = ;
+   nocdiv-cspdbgclk = ;
u-boot,dm-pre-reloc;
};
 
perpll {
+   vco0-psrc = ;
+   vco1-denom = ;
+   vco1-numer = ;
+   cntr2clk-cnt = ;
+   cntr2clk-src = ;
+   cntr3clk-cnt = ;
+   cntr3clk-src = ;
+   cntr4clk-cnt = ;
+   cntr4clk-src = ;
+   cntr5clk-cnt = ;
+   cntr5clk-src = ;
+   cntr6clk-cnt = ;
+   cntr6clk-src = ;
+   cntr7clk-cnt = ;
+   cntr8clk-cnt = ;
+   cntr8clk-src = ;
+   cntr9clk-cnt = ;
+   emacctl-emac0sel = ;
+   emacctl-emac1sel = ;
+   emacctl-emac2sel = ;
+   gpiodiv-gpiodbclk = ;
u-boot,dm-pre-reloc;
};
 
alteragrp {
+   nocclk = ;
+   mpuclk = ;
u-boot,dm-pre-reloc;
};
};
 
-   pinmux@0xffd07000 {
+   i_io48_pin_mux: pinmux@0xffd07000 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "pinctrl-single";
+   reg = <0xffd07000 0x0800>;
+   reg-names =