Re: [U-Boot] [PATCH 7/7] arm: v7R: Add support for enabling caches

[Lokesh Vutla]

On 4/25/2018 6:46 PM, Tom Rini wrote:
> On Wed, Apr 25, 2018 at 02:44:39PM +0530, Lokesh Vutla wrote:
> 
>> Cache maintenance procedure is same for v7A and v7R
>> processors. So re-use cache-cp15.c file except for
>> mmu parts.
> [snip]
>> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
>> index b09c631636..051f2789be 100644
>> --- a/arch/arm/lib/cache-cp15.c
>> +++ b/arch/arm/lib/cache-cp15.c
>> @@ -9,11 +9,15 @@
>>  #include 
>>  #include 
>>  #include 
>> +#ifdef CONFIG_SYS_ARM_MPU
>> +#include 
>> +#endif
> 
> Do we need to guard this include?
> 

Hmm..I guess it can be avoided. Will drop this and resend.

Thanks and regards,
Lokesh
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Re: [U-Boot] [PATCH 7/7] arm: v7R: Add support for enabling caches

[Tom Rini]

On Wed, Apr 25, 2018 at 02:44:39PM +0530, Lokesh Vutla wrote:

> Cache maintenance procedure is same for v7A and v7R
> processors. So re-use cache-cp15.c file except for
> mmu parts.
[snip]
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index b09c631636..051f2789be 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -9,11 +9,15 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_SYS_ARM_MPU
> +#include 
> +#endif

Do we need to guard this include?

-- 
Tom


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[U-Boot] [PATCH 7/7] arm: v7R: Add support for enabling caches

[Lokesh Vutla]

Cache maintenance procedure is same for v7A and v7R
processors. So re-use cache-cp15.c file except for
mmu parts.

Signed-off-by: Lokesh Vutla 
---
 arch/arm/cpu/armv7/mpu_v7r.c | 11 +++
 arch/arm/lib/cache-cp15.c| 14 +-
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c
index 5b6d21f29e..1862d5c3c7 100644
--- a/arch/arm/cpu/armv7/mpu_v7r.c
+++ b/arch/arm/cpu/armv7/mpu_v7r.c
@@ -107,3 +107,14 @@ void setup_mpu_regions(struct mpu_region_config *rgns, u32 
num_rgns)
 
icache_enable();
 }
+
+void enable_caches(void)
+{
+   /*
+* setup_mpu_regions() might have enabled Icache. So add a check
+* before enabling Icache
+*/
+   if (!icache_status())
+   icache_enable();
+   dcache_enable();
+}
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index b09c631636..051f2789be 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -9,11 +9,15 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_SYS_ARM_MPU
+#include 
+#endif
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_ARM_MMU
 __weak void arm_init_before_mmu(void)
 {
 }
@@ -202,15 +206,23 @@ static int mmu_enabled(void)
 {
return get_cr() & CR_M;
 }
+#endif /* CONFIG_SYS_ARM_MMU */
 
 /* cache_bit must be either CR_I or CR_C */
 static void cache_enable(uint32_t cache_bit)
 {
uint32_t reg;
 
-   /* The data cache is not active unless the mmu is enabled too */
+   /* The data cache is not active unless the mmu/mpu is enabled too */
+#ifdef CONFIG_SYS_ARM_MMU
if ((cache_bit == CR_C) && !mmu_enabled())
mmu_setup();
+#elif defined(CONFIG_SYS_ARM_MPU)
+   if ((cache_bit == CR_C) && !mpu_enabled()) {
+   printf("Consider enabling MPU before enabling caches\n");
+   return;
+   }
+#endif
reg = get_cr(); /* get control reg. */
set_cr(reg | cache_bit);
 }
-- 
2.17.0

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