Re: [U-Boot] [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR

[Mingkai Hu]

> -Original Message-
> From: Shaohui Xie
> Sent: Monday, August 29, 2016 12:45 PM
> To: york sun ; Qianyu Gong ;
> u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; Zhiqiang Hou ; Wenbin
> Song 
> Subject: RE: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR
> 
> > -Original Message-
> > From: york sun
> > Sent: Saturday, August 27, 2016 12:08 AM
> > To: Qianyu Gong ; u-boot@lists.denx.de
> > Cc: Prabhakar Kushwaha ; Mingkai Hu
> > ; Shaohui Xie ; Zhiqiang
> Hou
> > ; Wenbin Song 
> > Subject: Re: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR
> >
> > On 08/26/2016 04:40 AM, Gong Qianyu wrote:
> > > From: Shaohui Xie 
> > >
> > > So to fix SATA CRC error.
> >
> > Does ECC cause the CRC error? Please explain more what you are doing
> > in this patch.
> [S.H] We only know disable ECC can fix CRC error which provided by
> validation team As a workaround, the root cause is not clear.
> 
> Maybe we can drop it for now, there might be a better solution for this issue
> in future, or the solution is still the same, but we know exactly what is 
> going
> on.
> 
> Thanks,
> Shaohui

Maybe we keep this patch and add the description in the git log, and remove the
Disabling ECC when the root cause has found. At lease, disabling ECC can make 
the SATA working.

Thanks,
Mingkai

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR

[Shaohui Xie]

> -Original Message-
> From: york sun
> Sent: Saturday, August 27, 2016 12:08 AM
> To: Qianyu Gong ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; Shaohui Xie ; Zhiqiang Hou
> ; Wenbin Song 
> Subject: Re: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR
> 
> On 08/26/2016 04:40 AM, Gong Qianyu wrote:
> > From: Shaohui Xie 
> >
> > So to fix SATA CRC error.
> 
> Does ECC cause the CRC error? Please explain more what you are doing in this
> patch.
[S.H] We only know disable ECC can fix CRC error which provided by validation 
team
As a workaround, the root cause is not clear.

Maybe we can drop it for now, there might be a better solution for this issue 
in future, 
or the solution is still the same, but we know exactly what is going on.

Thanks,
Shaohui

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR

[york sun]

On 08/26/2016 04:40 AM, Gong Qianyu wrote:
> From: Shaohui Xie 
>
> So to fix SATA CRC error.

Does ECC cause the CRC error? Please explain more what you are doing in 
this patch.

York

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR

[Gong Qianyu]

From: Shaohui Xie 

So to fix SATA CRC error.

Signed-off-by: Shaohui Xie 
Signed-off-by: Gong Qianyu 
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..f1c6964 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -22,6 +22,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define SATA_ECC_REG_ADDR  0x20140520
+#define SATA_ECC_DISABLE   0x8000
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -222,6 +225,9 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
+#ifdef CONFIG_LS1046A
+   out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-- 
2.1.0.27.g96db324

___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot