Re: [U-Boot] [PATCH V2 05/18] OMAP5: palmas: Configure nominal opp vdd values
On Thu, Mar 01, 2012 at 08:08:30PM +0530, R Sricharan wrote: The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. OK, this creates some trivial conflicts with http://patchwork.ozlabs.org/patch/144137/ but also raises a functional problem / question. Is this patch also changing the order to match what Nishanth did or does this patch also need that functional change done (and a v3) ? Thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 05/18] OMAP5: palmas: Configure nominal opp vdd values
On Wed, Mar 7, 2012 at 11:04, Tom Rini tr...@ti.com wrote: On Thu, Mar 01, 2012 at 08:08:30PM +0530, R Sricharan wrote: The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. OK, this creates some trivial conflicts with http://patchwork.ozlabs.org/patch/144137/ but also raises a functional problem / question. Is this patch also changing the order to match what Nishanth did or does this patch also need that functional change done (and a v3) ? Thanks! Glancing at this patch, I see that scale sequence is still mpu, core, MM - which is what my sequence fixes. will be nice to have the sequence fixed followed by cleanup/update to retain the sequence appropriately. + /* Palmas settings */ + volt = VDD_MPU; + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - /* VCORE 1 - for vdd_core */ - volt = 1000; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + volt = VDD_MM; + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - /* VCORE 2 - for vdd_MM */ - volt = 1125; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + volt = VDD_CORE; + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); Regards, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 05/18] OMAP5: palmas: Configure nominal opp vdd values
On Wed, Mar 7, 2012 at 11:19 AM, Menon, Nishanth n...@ti.com wrote: On Wed, Mar 7, 2012 at 11:04, Tom Rini tr...@ti.com wrote: On Thu, Mar 01, 2012 at 08:08:30PM +0530, R Sricharan wrote: The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. OK, this creates some trivial conflicts with http://patchwork.ozlabs.org/patch/144137/ but also raises a functional problem / question. Is this patch also changing the order to match what Nishanth did or does this patch also need that functional change done (and a v3) ? Thanks! Glancing at this patch, I see that scale sequence is still mpu, core, MM - which is what my sequence fixes. will be nice to have the sequence fixed followed by cleanup/update to retain the sequence appropriately. + /* Palmas settings */ + volt = VDD_MPU; + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - /* VCORE 1 - for vdd_core */ - volt = 1000; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + volt = VDD_MM; + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - /* VCORE 2 - for vdd_MM */ - volt = 1125; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + volt = VDD_CORE; + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); I think what might be easiest all around is to drop Nishanth's 4/4 and have patch 5 here correct the order as well, crediting Nishanth for the fix. Alternatively, respin the series, depending on Nishanth's series being applied. Thanks. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 05/18] OMAP5: palmas: Configure nominal opp vdd values
On Wed, Mar 7, 2012 at 14:34, Tom Rini tr...@ti.com wrote: On Wed, Mar 7, 2012 at 11:19 AM, Menon, Nishanth n...@ti.com wrote: On Wed, Mar 7, 2012 at 11:04, Tom Rini tr...@ti.com wrote: On Thu, Mar 01, 2012 at 08:08:30PM +0530, R Sricharan wrote: The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. OK, this creates some trivial conflicts with http://patchwork.ozlabs.org/patch/144137/ but also raises a functional problem / question. Is this patch also changing the order to match what Nishanth did or does this patch also need that functional change done (and a v3) ? Thanks! Glancing at this patch, I see that scale sequence is still mpu, core, MM - which is what my sequence fixes. will be nice to have the sequence fixed followed by cleanup/update to retain the sequence appropriately. + /* Palmas settings */ + volt = VDD_MPU; + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - /* VCORE 1 - for vdd_core */ - volt = 1000; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + volt = VDD_MM; + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - /* VCORE 2 - for vdd_MM */ - volt = 1125; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + volt = VDD_CORE; + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); I think what might be easiest all around is to drop Nishanth's 4/4 and have patch 5 here correct the order as well, crediting Nishanth for the fix. Alternatively, respin the series, depending on Nishanth's series being applied. Thanks. ok with either. might be good to merge my patch 5 here so that #patches are reduced :) Regards, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 05/18] OMAP5: palmas: Configure nominal opp vdd values
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 15 +++
arch/arm/cpu/armv7/omap4/clocks.c | 15 +++
arch/arm/cpu/armv7/omap5/clocks.c | 31 +---
arch/arm/include/asm/arch-omap4/clocks.h |1 +
arch/arm/include/asm/arch-omap5/clocks.h | 16
5 files changed, 53 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 20029b5..cc4e538 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -390,23 +390,16 @@ void do_scale_tps62361(u32 reg, u32 volt_mv)
void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
{
u32 temp, offset_code;
- u32 step = 12660; /* 12.66 mV represented in uV */
+
u32 offset = volt_mv;
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
- if (omap_revision() == OMAP4430_ES1_0)
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
- else
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
- offset_code = (offset + step - 1) / step;
- /* The code starts at 1 not 0 */
- offset_code++;
+ offset_code = get_offset_code(offset);
- debug(do_scale_vcore: volt - %d offset_code - 0x%x\n, volt_mv,
- offset_code);
+ debug(do_scale_vcore: vcore_reg - 0x%x volt - %d offset_code - 0x%x\n,
+ vcore_reg, volt_mv, offset_code);
temp = SMPS_I2C_SLAVE_ADDR |
(vcore_reg PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c
b/arch/arm/cpu/armv7/omap4/clocks.c
index e2189f7..98e179d 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -318,6 +318,21 @@ void scale_vcores(void)
}
}
+u32 get_offset_code(u32 offset)
+{
+ u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
+
+ if (omap_revision() == OMAP4430_ES1_0)
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+ else
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+ offset_code = (offset + step - 1) / step;
+
+ /* The code starts at 1 not 0 */
+ return ++offset_code;
+}
+
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c
b/arch/arm/cpu/armv7/omap5/clocks.c
index 4d1bc56..8c010d4 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -264,17 +264,30 @@ void scale_vcores(void)
setup_sri2c();
- /* Enable 1.22V from TPS for vdd_mpu */
- volt = 1220;
- do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+ /* Palmas settings */
+ volt = VDD_MPU;
+ do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
- /* VCORE 1 - for vdd_core */
- volt = 1000;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+ volt = VDD_MM;
+ do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
- /* VCORE 2 - for vdd_MM */
- volt = 1125;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+ volt = VDD_CORE;
+ do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
+}
+
+u32 get_offset_code(u32 volt_offset)
+{
+ u32 offset_code, step = 1; /* 10 mV represented in uV */
+
+ volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
+
+ offset_code = (volt_offset + step - 1) / step;
+
+ /*
+* Offset codes 1-6 all give the base voltage in Palmas
+* Offset code 0 switches OFF the SMPS
+*/
+ return offset_code + 6;
}
/*
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h
b/arch/arm/include/asm/arch-omap4/clocks.h
index cd304e8..e52595b 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -754,6 +754,7 @@ extern struct omap4_prcm_regs *const prcm;
extern const u32 sys_clk_array[8];
void scale_vcores(void);
+u32 get_offset_code(u32 offset);
void do_scale_tps62361(u32 reg, u32 volt_mv);
u32 omap_ddr_clk(void);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h
b/arch/arm/include/asm/arch-omap5/clocks.h
index faed887..b36638e 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -647,12 +647,17 @@ struct omap5_prcm_regs {
/* SMPS */
#define SMPS_I2C_SLAVE_ADDR0x12
-#define SMPS_REG_ADDR_VCORE1 0x55
-#define SMPS_REG_ADDR_VCORE2 0x5B
-#define SMPS_REG_ADDR_VCORE3 0x61
+#define SMPS_REG_ADDR_12_MPU 0x23
+#define SMPS_REG_ADDR_45_IVA 0x2B
+#define SMPS_REG_ADDR_8_CORE 0x37
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
