Re: [U-Boot] [PATCH V2 1/3] sunxi: Use clrsetbits_le32 instead of multiple instruction

2019-02-18 Thread Jagan Teki 
On Thu, Feb 14, 2019 at 9:28 PM Michael Trimarchi
 wrote:
>
> Signed-off-by: Michael Trimarchi 
> ---
>
> V1->V2: none
>
> ---
>  arch/arm/mach-sunxi/dram_sun8i_a33.c | 8 ++--
>  1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c 
> b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> index 1da2727f98..83212aaddf 100644
> --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
> +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
> @@ -148,12 +148,8 @@ static void auto_set_timing_para(struct dram_para *para)
> reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 
> 0);
> writel(reg_val, &mctl_ctl->dramtmg5);
> /* Set two rank timing and exit self-refresh timing */
> -   reg_val = readl(&mctl_ctl->dramtmg8);
> -   reg_val &= ~(0xff << 8);
> -   reg_val &= ~(0xff << 0);

these are clr

> -   reg_val |= (0x33 << 8);
> -   reg_val |= (0x8 << 0);

these are set

> -   writel(reg_val, &mctl_ctl->dramtmg8);
> +   clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0),
> +   0x33 << 8 | (0x8 << 0));
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[U-Boot] [PATCH V2 1/3] sunxi: Use clrsetbits_le32 instead of multiple instruction

2019-02-14 Thread Michael Trimarchi 
Signed-off-by: Michael Trimarchi 
---

V1->V2: none

---
 arch/arm/mach-sunxi/dram_sun8i_a33.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c 
b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index 1da2727f98..83212aaddf 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
@@ -148,12 +148,8 @@ static void auto_set_timing_para(struct dram_para *para)
reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
writel(reg_val, &mctl_ctl->dramtmg5);
/* Set two rank timing and exit self-refresh timing */
-   reg_val = readl(&mctl_ctl->dramtmg8);
-   reg_val &= ~(0xff << 8);
-   reg_val &= ~(0xff << 0);
-   reg_val |= (0x33 << 8);
-   reg_val |= (0x8 << 0);
-   writel(reg_val, &mctl_ctl->dramtmg8);
+   clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0),
+   0x33 << 8 | (0x8 << 0));
/* Set phy interface time */
reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
| (wr_latency << 0);
-- 
2.17.1

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