Re: [U-Boot] [PATCH V2 3/4] ARM: mx6: Add PCI express driver
Hi Marek, On 14/12/2013 05:55, Marek Vasut wrote: Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic Applied to u-boot-imx, thanks ! Best regards, Stefano Babic - = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 3/4] ARM: mx6: Add PCI express driver
On Saturday, December 14, 2013 at 09:52:21 AM, Jagan Teki wrote:
> On Sat, Dec 14, 2013 at 11:03 AM, Marek Vasut wrote:
> > On Saturday, December 14, 2013 at 06:23:30 AM, Jagan Teki wrote:
> > [...]
> >
> >> > +/*
> >> > + * Replace the original ARM DABT handler with a simple jump-back one.
> >> > + *
> >> > + * The problem here is that if we have a PCIe bridge attached to this
> >> > PCIe + * controller, but no PCIe device is connected to the bridges'
> >> > downstream + * port, the attempt to read/write from/to the config
> >> > space will produce + * a DABT. This is a behavior of the controller
> >> > and can not be disabled + * unfortuatelly.
> >> > + *
> >> > + * To work around the problem, we backup the current DABT handler
> >> > address + * and replace it with our own DABT handler, which only
> >> > bounces right back + * into the code.
> >> > + */
> >> > +static void imx_pcie_fix_dabt_handler(bool set)
> >> > +{
> >> > + extern uint32_t *_data_abort;
> >>
> >> Not a good idea to use extern in .c - any comments?
> >
> > Why is half of the CC dropped from this email? (restored by hand)
>
> Sorry, some accident.
>
> > As for the extern, there is no better way to replace the DABT handler
> > (see patch 0001) for this purpose . This will be changed later though,
> > once Alberts' patches land , but that's a post-2014.01 matter.
>
> OK.
>
> And one more thing, where is the patch V2, 1/4 - I couldn't find it.
Nowhere, 1/4 didn't change.
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH V2 3/4] ARM: mx6: Add PCI express driver
On Sat, Dec 14, 2013 at 11:03 AM, Marek Vasut wrote:
> On Saturday, December 14, 2013 at 06:23:30 AM, Jagan Teki wrote:
> [...]
>> > +/*
>> > + * Replace the original ARM DABT handler with a simple jump-back one.
>> > + *
>> > + * The problem here is that if we have a PCIe bridge attached to this
>> > PCIe + * controller, but no PCIe device is connected to the bridges'
>> > downstream + * port, the attempt to read/write from/to the config space
>> > will produce + * a DABT. This is a behavior of the controller and can
>> > not be disabled + * unfortuatelly.
>> > + *
>> > + * To work around the problem, we backup the current DABT handler
>> > address + * and replace it with our own DABT handler, which only bounces
>> > right back + * into the code.
>> > + */
>> > +static void imx_pcie_fix_dabt_handler(bool set)
>> > +{
>> > + extern uint32_t *_data_abort;
>>
>> Not a good idea to use extern in .c - any comments?
>
> Why is half of the CC dropped from this email? (restored by hand)
Sorry, some accident.
>
> As for the extern, there is no better way to replace the DABT handler (see
> patch
> 0001) for this purpose . This will be changed later though, once Alberts'
> patches land , but that's a post-2014.01 matter.
OK.
And one more thing, where is the patch V2, 1/4 - I couldn't find it.
--
Thanks,
Jagan.
Jagannadha Sutradharudu Teki,
E: jagannadh.t...@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki
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Re: [U-Boot] [PATCH V2 3/4] ARM: mx6: Add PCI express driver
On Saturday, December 14, 2013 at 06:23:30 AM, Jagan Teki wrote:
[...]
> > +/*
> > + * Replace the original ARM DABT handler with a simple jump-back one.
> > + *
> > + * The problem here is that if we have a PCIe bridge attached to this
> > PCIe + * controller, but no PCIe device is connected to the bridges'
> > downstream + * port, the attempt to read/write from/to the config space
> > will produce + * a DABT. This is a behavior of the controller and can
> > not be disabled + * unfortuatelly.
> > + *
> > + * To work around the problem, we backup the current DABT handler
> > address + * and replace it with our own DABT handler, which only bounces
> > right back + * into the code.
> > + */
> > +static void imx_pcie_fix_dabt_handler(bool set)
> > +{
> > + extern uint32_t *_data_abort;
>
> Not a good idea to use extern in .c - any comments?
Why is half of the CC dropped from this email? (restored by hand)
As for the extern, there is no better way to replace the DABT handler (see
patch
0001) for this purpose . This will be changed later though, once Alberts'
patches land , but that's a post-2014.01 matter.
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH V2 3/4] ARM: mx6: Add PCI express driver
On Sat, Dec 14, 2013 at 10:25 AM, Marek Vasut wrote: > Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the > PCIe block in RC mode only, the EP mode is NOT supported. The driver is > tested with the Intel e1000 NIC driver. > > Signed-off-by: Marek Vasut > Cc: Albert Aribaud > Cc: Eric Nelson > Cc: Fabio Estevam > Cc: Stefano Babic > --- > arch/arm/include/asm/arch-mx6/iomux.h | 27 ++ > drivers/pci/Makefile | 1 + > drivers/pci/pcie_imx.c| 565 > ++ > 3 files changed, 593 insertions(+) > create mode 100644 drivers/pci/pcie_imx.c > > V2: - Check for link_in_training bit while waiting for LTSSM to finish. > - Replace udelay(3) with mdelay(30) in the core reset end seq. > - Check if the link-up failed and don't probe the bus in such case > to prevent a hang. > - Do not assert LTSSM while the DWC core is in reset (thanks for finding > this, Richard Zhu) > > diff --git a/arch/arm/include/asm/arch-mx6/iomux.h > b/arch/arm/include/asm/arch-mx6/iomux.h > index fe4675e..f9ee0d9 100644 > --- a/arch/arm/include/asm/arch-mx6/iomux.h > +++ b/arch/arm/include/asm/arch-mx6/iomux.h > @@ -15,6 +15,33 @@ > #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) > #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) > #define IOMUXC_GPR1_OTG_ID_MASK(1<<13) > +#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) > +#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) > + > +/* > + * IOMUXC_GPR8 bit fields > + */ > +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK(0x3f << 0) > +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 > +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) > +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET6 > +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK(0x3f << 12) > +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 > +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) > +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 > +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) > +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET25 > + > +/* > + * IOMUXC_GPR12 bit fields > + */ > +#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) > +#define IOMUXC_GPR12_LOS_LEVEL_MASK(0x1f << 4) > +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) > +#define IOMUXC_GPR12_DEVICE_TYPE_EP(0x0 << 12) > +#define IOMUXC_GPR12_DEVICE_TYPE_RC(0x2 << 12) > +#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) > + > /* > * IOMUXC_GPR13 bit fields > */ > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > index 99d51a6..565ff37 100644 > --- a/drivers/pci/Makefile > +++ b/drivers/pci/Makefile > @@ -9,6 +9,7 @@ obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o > obj-$(CONFIG_PCI) += pci.o pci_auto.o > obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o > obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o > +obj-$(CONFIG_PCIE_IMX) += pcie_imx.o > obj-$(CONFIG_FTPCI100) += pci_ftpci100.o > obj-$(CONFIG_IXP_PCI) += pci_ixp.o > obj-$(CONFIG_SH4_PCI) += pci_sh4.o > diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c > new file mode 100644 > index 000..0a74867 > --- /dev/null > +++ b/drivers/pci/pcie_imx.c > @@ -0,0 +1,565 @@ > +/* > + * Freescale i.MX6 PCI Express Root-Complex driver > + * > + * Copyright (C) 2013 Marek Vasut > + * > + * Based on upstream Linux kernel driver: > + * pci-imx6.c: Sean Cross > + * pcie-designware.c: Jingoo Han > + * > + * SPDX-License-Identifier:GPL-2.0 > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define PCI_ACCESS_READ 0 > +#define PCI_ACCESS_WRITE 1 > + > +#define MX6_DBI_ADDR 0x01ffc000 > +#define MX6_DBI_SIZE 0x4000 > +#define MX6_IO_ADDR0x0100 > +#define MX6_IO_SIZE0x10 > +#define MX6_MEM_ADDR 0x0110 > +#define MX6_MEM_SIZE 0xe0 > +#define MX6_ROOT_ADDR 0x01f0 > +#define MX6_ROOT_SIZE 0xfc000 > + > +/* PCIe Port Logic registers (memory-mapped) */ > +#define PL_OFFSET 0x700 > +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) > +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) > +#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) > +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) > + > +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) > +#define PCIE_PHY_CTRL_DATA_LOC 0 > +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 > +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 > +#define PCIE_PHY_CTRL_WR_LOC 18 > +#define PCIE_PHY_CTRL_RD_LOC 19 > + > +#define PCIE_PHY_STAT (PL_OFFSET + 0x110) > +#define PCIE_PHY_STAT_DATA_LOC 0 > +#define PCIE_PHY_STAT_ACK_LOC 16 > + > +/* PHY registers (not memory-mapped) */ > +#define PCIE_PHY_RX_ASIC_OUT 0x100D > + > +#define PHY_RX_OVRD_IN_LO 0x1005 > +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) > +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) > +
[U-Boot] [PATCH V2 3/4] ARM: mx6: Add PCI express driver
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the PCIe block in RC mode only, the EP mode is NOT supported. The driver is tested with the Intel e1000 NIC driver. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/include/asm/arch-mx6/iomux.h | 27 ++ drivers/pci/Makefile | 1 + drivers/pci/pcie_imx.c| 565 ++ 3 files changed, 593 insertions(+) create mode 100644 drivers/pci/pcie_imx.c V2: - Check for link_in_training bit while waiting for LTSSM to finish. - Replace udelay(3) with mdelay(30) in the core reset end seq. - Check if the link-up failed and don't probe the bus in such case to prevent a hang. - Do not assert LTSSM while the DWC core is in reset (thanks for finding this, Richard Zhu) diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index fe4675e..f9ee0d9 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -15,6 +15,33 @@ #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13) #define IOMUXC_GPR1_OTG_ID_GPIO1 (1<<13) #define IOMUXC_GPR1_OTG_ID_MASK(1<<13) +#define IOMUXC_GPR1_REF_SSP_EN (1 << 16) +#define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) + +/* + * IOMUXC_GPR8 bit fields + */ +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK(0x3f << 0) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET 0 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << 6) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET6 +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK(0x3f << 12) +#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET 12 +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK (0x7f << 18) +#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET 18 +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK (0x7f << 25) +#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET25 + +/* + * IOMUXC_GPR12 bit fields + */ +#define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) +#define IOMUXC_GPR12_LOS_LEVEL_MASK(0x1f << 4) +#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) +#define IOMUXC_GPR12_DEVICE_TYPE_EP(0x0 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC(0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) + /* * IOMUXC_GPR13 bit fields */ diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 99d51a6..565ff37 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI) += pci.o pci_auto.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o +obj-$(CONFIG_PCIE_IMX) += pcie_imx.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_IXP_PCI) += pci_ixp.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c new file mode 100644 index 000..0a74867 --- /dev/null +++ b/drivers/pci/pcie_imx.c @@ -0,0 +1,565 @@ +/* + * Freescale i.MX6 PCI Express Root-Complex driver + * + * Copyright (C) 2013 Marek Vasut + * + * Based on upstream Linux kernel driver: + * pci-imx6.c: Sean Cross + * pcie-designware.c: Jingoo Han + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define MX6_DBI_ADDR 0x01ffc000 +#define MX6_DBI_SIZE 0x4000 +#define MX6_IO_ADDR0x0100 +#define MX6_IO_SIZE0x10 +#define MX6_MEM_ADDR 0x0110 +#define MX6_MEM_SIZE 0xe0 +#define MX6_ROOT_ADDR 0x01f0 +#define MX6_ROOT_SIZE 0xfc000 + +/* PCIe Port Logic registers (memory-mapped) */ +#define PL_OFFSET 0x700 +#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) +#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) + +#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) +#define PCIE_PHY_CTRL_DATA_LOC 0 +#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 +#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 +#define PCIE_PHY_CTRL_WR_LOC 18 +#define PCIE_PHY_CTRL_RD_LOC 19 + +#define PCIE_PHY_STAT (PL_OFFSET + 0x110) +#define PCIE_PHY_STAT_DATA_LOC 0 +#define PCIE_PHY_STAT_ACK_LOC 16 + +/* PHY registers (not memory-mapped) */ +#define PCIE_PHY_RX_ASIC_OUT 0x100D + +#define PHY_RX_OVRD_IN_LO 0x1005 +#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) +#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND(0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#
