RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.
Signed-off-by: Nishanth Menon
---
arch/arm/cpu/armv7/omap3/board.c| 45 ---
arch/arm/include/asm/arch-omap3/sys_proto.h |1 +
board/nokia/rx51/rx51.c | 19 ++-
include/configs/nokia_rx51.h|4 +++
4 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 51a1c5816c3e..b064c0cc8343 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -415,31 +415,30 @@ static void omap3_emu_romcode_call(u32 service_id, u32
*parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
- u32 cpu_variant, u32 cpu_rev)
+void __weak omap3_set_aux_cr_secure(u32 acr)
{
- if (get_device_type() == GP_DEVICE) {
- omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
- } else {
- struct emu_hal_params emu_romcode_params;
- emu_romcode_params.num_params = 1;
- emu_romcode_params.param1 = acr;
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
- }
+ struct emu_hal_params emu_romcode_params;
+
+ emu_romcode_params.num_params = 1;
+ emu_romcode_params.param1 = acr;
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
}
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
{
- u32 acr;
+ /* Write ACR - affects secure banked bits */
+ if (get_device_type() == GP_DEVICE)
+ omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
+ else
+ omap3_set_aux_cr_secure(acr);
- /* Read ACR */
- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
- acr &= ~clear_bits;
- acr |= set_bits;
- v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
+ /* Write ACR - affects non-secure banked bits - some erratas need it */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
+
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
@@ -449,9 +448,8 @@ static void omap3_update_aux_cr(u32 set_bits, u32
clear_bits)
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
+ v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
- /* Write ACR - affects non-secure banked bits */
- asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
/* Invalidate the entire L2 cache from secure mode */
@@ -470,10 +468,9 @@ static void omap3_invalidate_l2_cache_secure(void)
void v7_outer_cache_enable(void)
{
- /* Set L2EN */
- omap3_update_aux_cr_secure(0x2, 0);
/*
+* Set L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in setting both banked bits(in fact this is required
* by an erratum)
@@ -483,10 +480,8 @@ void v7_outer_cache_enable(void)
void omap3_outer_cache_disable(void)
{
- /* Clear L2EN */
- omap3_update_aux_cr_secure(0, 0x2);
-
/*
+* Clear L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in clearing both banked bits(in fact this is required
* by an erratum)
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 0c77a22ccfff..3e45ce184ba4 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -73,5 +73,6 @@ void power_init_r(void);
void dieid_num_r(void);
void get_dieid(u32 *id);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
+void omap3_set_aux_cr_secure(u32 acr);
u32 warm_reset(void);
#endif
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 08fcaf21b3c6..3d019b01428b 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -341,6 +341,17 @@ static void omap3_emu_romcode_call(u32 service_id, u32
*parameters)
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
+void omap3_set_aux_cr_secure(u32 acr)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+
