Re: [U-Boot] [PATCH v1 02/18] MIPS: initial infrastructure for Microchip PIC32 architecture.

[Purna Chandra Mandal]

On 12/21/2015 10:31 PM, Daniel Schwierzeck wrote:

>
> Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:
>> Signed-off-by: Purna Chandra Mandal 
>> ---
>>
>>  arch/mips/Kconfig|   5 ++
>>  arch/mips/Makefile   |   1 +
>>  arch/mips/include/asm/arch-pic32/clock.h |  31 +++
>>  arch/mips/include/asm/arch-pic32/pic32.h | 145 
>> +++
>>  arch/mips/mach-pic32/Kconfig |  20 +
>>  arch/mips/mach-pic32/Makefile|   7 ++
>>  arch/mips/mach-pic32/config.mk   |   8 ++
>>  arch/mips/mach-pic32/cpu.c   |  13 +++
>>  8 files changed, 230 insertions(+)
>>  create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
>>  create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
> I noticed in an other thread that CONFIG_ARCH_SYMLINKS is going to be
> deprecated. The preferred location for SoC specific header files is
> "arch/*/mach-*/include/mach/". A driver can then use "include
> ".
>
> I've already sent a patch for MIPS [1]. So please rebase to
> u-boot-mips/next and move those two files to
> arch/mips/mach-pic32/include/mach/.

Thanks. Will rebase and update accordingly.

>>  create mode 100644 arch/mips/mach-pic32/Kconfig
>>  create mode 100644 arch/mips/mach-pic32/Makefile
>>  create mode 100644 arch/mips/mach-pic32/config.mk
>>  create mode 100644 arch/mips/mach-pic32/cpu.c
>>
> [1] http://patchwork.ozlabs.org/patch/559581/
>

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Re: [U-Boot] [PATCH v1 02/18] MIPS: initial infrastructure for Microchip PIC32 architecture.

[Purna Chandra Mandal]

On 12/20/2015 04:49 AM, Daniel Schwierzeck wrote:
>
> Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:
>> Signed-off-by: Purna Chandra Mandal 
>> ---
>>
>>  arch/mips/Kconfig|   5 ++
>>  arch/mips/Makefile   |   1 +
>>  arch/mips/include/asm/arch-pic32/clock.h |  31 +++
>>  arch/mips/include/asm/arch-pic32/pic32.h | 145 
>> +++
>>  arch/mips/mach-pic32/Kconfig |  20 +
>>  arch/mips/mach-pic32/Makefile|   7 ++
>>  arch/mips/mach-pic32/config.mk   |   8 ++
>>  arch/mips/mach-pic32/cpu.c   |  13 +++
>>  8 files changed, 230 insertions(+)
>>  create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
>>  create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
>>  create mode 100644 arch/mips/mach-pic32/Kconfig
>>  create mode 100644 arch/mips/mach-pic32/Makefile
>>  create mode 100644 arch/mips/mach-pic32/config.mk
>>  create mode 100644 arch/mips/mach-pic32/cpu.c
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 7f7e258..2a707e2 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -51,6 +51,10 @@ config TARGET_PB1X00
>>  select SUPPORTS_CPU_MIPS32_R2
>>  select SYS_MIPS_CACHE_INIT_RAM_LOAD
>>  
>> +config MACH_PIC32
>> +bool "Support Microchip PIC32"
>> +select OF_CONTROL
>> +select DM
>>  
>>  endchoice
>>  
>> @@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
>>  source "board/micronas/vct/Kconfig"
>>  source "board/pb1x00/Kconfig"
>>  source "board/qemu-mips/Kconfig"
>> +source "arch/mips/mach-pic32/Kconfig"
>>  
>>  if MIPS
>>  
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index 43f0f5c..8b7c7e3 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
>>  libs-y += arch/mips/lib/
>>  
>>  libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
>> +libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/
>> diff --git a/arch/mips/include/asm/arch-pic32/clock.h 
>> b/arch/mips/include/asm/arch-pic32/clock.h
>> new file mode 100644
>> index 000..6a4270d
>> --- /dev/null
>> +++ b/arch/mips/include/asm/arch-pic32/clock.h
>> @@ -0,0 +1,31 @@
>> +/*
>> + * (c) 2015 Purna Chandra Mandal purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +
>> +#ifndef __PIC32_CLOCK_H_
>> +#define __PIC32_CLOCK_H_
>> +
>> +/* clk */
>> +enum {
>> +BASECLK,
>> +PLLCLK,
>> +MPLL,
>> +SYSCLK,
>> +PB1CLK,
>> +PB2CLK,
>> +PB3CLK,
>> +PB4CLK,
>> +PB5CLK,
>> +PB6CLK,
>> +PB7CLK,
>> +REF1CLK,
>> +REF2CLK,
>> +REF3CLK,
>> +REF4CLK,
>> +REF5CLK,
>> +};
>> +
>> +#endif/* __PIC32_CLOCK_H_ */
>> diff --git a/arch/mips/include/asm/arch-pic32/pic32.h 
>> b/arch/mips/include/asm/arch-pic32/pic32.h
>> new file mode 100644
>> index 000..4f2084f
>> --- /dev/null
>> +++ b/arch/mips/include/asm/arch-pic32/pic32.h
>> @@ -0,0 +1,145 @@
>> +/*
>> + * (c) 2015 Paul Thacker 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +
>> +#ifndef __PIC32_REGS_H__
>> +#define __PIC32_REGS_H__
>> +
>> +#define _CLR_OFFSET(0x4)
>> +#define _SET_OFFSET(0x8)
>> +#define _INV_OFFSET(0xc)
>> +
>> +/* System Configuration */
>> +#define PIC32_CFG_BASE(x) 0xbf80
> you should a base address as physical address as seen by the CPU (e.g.
> 0x1f80). The driver then does a remap to KSEG1. But if you use
> device-tree, you should get base address and size of a register space
> from there. Example:
>
> void __iomem *base = (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE)

ack. will update.

>> +#define CFGCON(PIC32_CFG_BASE(x))
>> +#define DEVID(PIC32_CFG_BASE(x) + 0x0020)
>> +#define SYSKEY(PIC32_CFG_BASE(x) + 0x0030)
>> +#define PMD1(PIC32_CFG_BASE(x) + 0x0040)
>> +#define PMD7(PIC32_CFG_BASE(x) + 0x00a0)
>> +#define CFGEBIA(PIC32_CFG_BASE(x) + 0x00c0)
>> +#define CFGEBIC(PIC32_CFG_BASE(x) + 0x00d0)
>> +#define CFGPG(PIC32_CFG_BASE(x) + 0x00e0)
>> +#define CFGMPLL(PIC32_CFG_BASE(x) + 0x0100)
> registers should only defined by their relative offset. The addition to
> the base address is not needed. A driver could do:
>
> readl(base + CFGCON)

ack.

>> +
>> +/* Clock & Reset */
>> +#define RESET_BASE0xbf80
>> +
>> +/* Non Volatile Memory (NOR flash) */
>> +#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
>> +
>> +/* Reset Control Registers */
>> +#define RSWRST(RESET_BASE + 0x1250)
>> +
>> +/* Oscillator Configuration */
>> +#define OSCCON(RESET_BASE + 0x1200)
>> +#define SPLLCON(RESET_BASE + 0x1220)
>> +#define REFO1CON(RESET_BASE + 0x1280)
>> +#define REFO1TRIM(RESET_BASE + 0x1290)
>> +#define PB1DIV(RESET_BASE + 0x1340)
>> +
>> +/* Peripheral PORTA-PORTK / PORT0-PORT9 */
>> +enum {
>> +PIC32_PORT_A = 0,
>> +

Re: [U-Boot] [PATCH v1 02/18] MIPS: initial infrastructure for Microchip PIC32 architecture.

[Purna Chandra Mandal]

On 12/20/2015 04:49 AM, Daniel Schwierzeck wrote:
>
> Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:
>> Signed-off-by: Purna Chandra Mandal 
>> ---
>>
>>  arch/mips/Kconfig|   5 ++
>>  arch/mips/Makefile   |   1 +
>>  arch/mips/include/asm/arch-pic32/clock.h |  31 +++
>>  arch/mips/include/asm/arch-pic32/pic32.h | 145 
>> +++
>>  arch/mips/mach-pic32/Kconfig |  20 +
>>  arch/mips/mach-pic32/Makefile|   7 ++
>>  arch/mips/mach-pic32/config.mk   |   8 ++
>>  arch/mips/mach-pic32/cpu.c   |  13 +++
>>  8 files changed, 230 insertions(+)
>>  create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
>>  create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
>>  create mode 100644 arch/mips/mach-pic32/Kconfig
>>  create mode 100644 arch/mips/mach-pic32/Makefile
>>  create mode 100644 arch/mips/mach-pic32/config.mk
>>  create mode 100644 arch/mips/mach-pic32/cpu.c
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 7f7e258..2a707e2 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -51,6 +51,10 @@ config TARGET_PB1X00
>>  select SUPPORTS_CPU_MIPS32_R2
>>  select SYS_MIPS_CACHE_INIT_RAM_LOAD
>>  
>> +config MACH_PIC32
>> +bool "Support Microchip PIC32"
>> +select OF_CONTROL
>> +select DM
>>  
>>  endchoice
>>  
>> @@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
>>  source "board/micronas/vct/Kconfig"
>>  source "board/pb1x00/Kconfig"
>>  source "board/qemu-mips/Kconfig"
>> +source "arch/mips/mach-pic32/Kconfig"
>>  
>>  if MIPS
>>  
>> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
>> index 43f0f5c..8b7c7e3 100644
>> --- a/arch/mips/Makefile
>> +++ b/arch/mips/Makefile
>> @@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
>>  libs-y += arch/mips/lib/
>>  
>>  libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
>> +libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/
>> diff --git a/arch/mips/include/asm/arch-pic32/clock.h 
>> b/arch/mips/include/asm/arch-pic32/clock.h
>> new file mode 100644
>> index 000..6a4270d
>> --- /dev/null
>> +++ b/arch/mips/include/asm/arch-pic32/clock.h
>> @@ -0,0 +1,31 @@
>> +/*
>> + * (c) 2015 Purna Chandra Mandal purna.man...@microchip.com>
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +
>> +#ifndef __PIC32_CLOCK_H_
>> +#define __PIC32_CLOCK_H_
>> +
>> +/* clk */
>> +enum {
>> +BASECLK,
>> +PLLCLK,
>> +MPLL,
>> +SYSCLK,
>> +PB1CLK,
>> +PB2CLK,
>> +PB3CLK,
>> +PB4CLK,
>> +PB5CLK,
>> +PB6CLK,
>> +PB7CLK,
>> +REF1CLK,
>> +REF2CLK,
>> +REF3CLK,
>> +REF4CLK,
>> +REF5CLK,
>> +};
>> +
>> +#endif/* __PIC32_CLOCK_H_ */
>> diff --git a/arch/mips/include/asm/arch-pic32/pic32.h 
>> b/arch/mips/include/asm/arch-pic32/pic32.h
>> new file mode 100644
>> index 000..4f2084f
>> --- /dev/null
>> +++ b/arch/mips/include/asm/arch-pic32/pic32.h
>> @@ -0,0 +1,145 @@
>> +/*
>> + * (c) 2015 Paul Thacker 
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + *
>> + */
>> +
>> +#ifndef __PIC32_REGS_H__
>> +#define __PIC32_REGS_H__
>> +
>> +#define _CLR_OFFSET(0x4)
>> +#define _SET_OFFSET(0x8)
>> +#define _INV_OFFSET(0xc)
>> +
>> +/* System Configuration */
>> +#define PIC32_CFG_BASE(x) 0xbf80
> you should a base address as physical address as seen by the CPU (e.g.
> 0x1f80). The driver then does a remap to KSEG1. But if you use
> device-tree, you should get base address and size of a register space
> from there. Example:
>
> void __iomem *base = (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE)

ack. Will update.

>> +#define CFGCON(PIC32_CFG_BASE(x))
>> +#define DEVID(PIC32_CFG_BASE(x) + 0x0020)
>> +#define SYSKEY(PIC32_CFG_BASE(x) + 0x0030)
>> +#define PMD1(PIC32_CFG_BASE(x) + 0x0040)
>> +#define PMD7(PIC32_CFG_BASE(x) + 0x00a0)
>> +#define CFGEBIA(PIC32_CFG_BASE(x) + 0x00c0)
>> +#define CFGEBIC(PIC32_CFG_BASE(x) + 0x00d0)
>> +#define CFGPG(PIC32_CFG_BASE(x) + 0x00e0)
>> +#define CFGMPLL(PIC32_CFG_BASE(x) + 0x0100)
> registers should only defined by their relative offset. The addition to
> the base address is not needed. A driver could do:
>
> readl(base + CFGCON)

ack.

>> +
>> +/* Clock & Reset */
>> +#define RESET_BASE0xbf80
>> +
>> +/* Non Volatile Memory (NOR flash) */
>> +#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
>> +
>> +/* Reset Control Registers */
>> +#define RSWRST(RESET_BASE + 0x1250)
>> +
>> +/* Oscillator Configuration */
>> +#define OSCCON(RESET_BASE + 0x1200)
>> +#define SPLLCON(RESET_BASE + 0x1220)
>> +#define REFO1CON(RESET_BASE + 0x1280)
>> +#define REFO1TRIM(RESET_BASE + 0x1290)
>> +#define PB1DIV(RESET_BASE + 0x1340)
>> +
>> +/* Peripheral PORTA-PORTK / PORT0-PORT9 */
>> +enum {
>> +PIC32_PORT_A = 0,
>> +

Re: [U-Boot] [PATCH v1 02/18] MIPS: initial infrastructure for Microchip PIC32 architecture.

[Daniel Schwierzeck]

Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:
> 
> Signed-off-by: Purna Chandra Mandal 
> ---
> 
>  arch/mips/Kconfig|   5 ++
>  arch/mips/Makefile   |   1 +
>  arch/mips/include/asm/arch-pic32/clock.h |  31 +++
>  arch/mips/include/asm/arch-pic32/pic32.h | 145 
> +++
>  arch/mips/mach-pic32/Kconfig |  20 +
>  arch/mips/mach-pic32/Makefile|   7 ++
>  arch/mips/mach-pic32/config.mk   |   8 ++
>  arch/mips/mach-pic32/cpu.c   |  13 +++
>  8 files changed, 230 insertions(+)
>  create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
>  create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h

I noticed in an other thread that CONFIG_ARCH_SYMLINKS is going to be
deprecated. The preferred location for SoC specific header files is
"arch/*/mach-*/include/mach/". A driver can then use "include
".

I've already sent a patch for MIPS [1]. So please rebase to
u-boot-mips/next and move those two files to
arch/mips/mach-pic32/include/mach/.

>  create mode 100644 arch/mips/mach-pic32/Kconfig
>  create mode 100644 arch/mips/mach-pic32/Makefile
>  create mode 100644 arch/mips/mach-pic32/config.mk
>  create mode 100644 arch/mips/mach-pic32/cpu.c
> 

[1] http://patchwork.ozlabs.org/patch/559581/

-- 
- Daniel
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Re: [U-Boot] [PATCH v1 02/18] MIPS: initial infrastructure for Microchip PIC32 architecture.

[Daniel Schwierzeck]

Am 17.12.2015 um 18:28 schrieb Purna Chandra Mandal:
> 
> Signed-off-by: Purna Chandra Mandal 
> ---
> 
>  arch/mips/Kconfig|   5 ++
>  arch/mips/Makefile   |   1 +
>  arch/mips/include/asm/arch-pic32/clock.h |  31 +++
>  arch/mips/include/asm/arch-pic32/pic32.h | 145 
> +++
>  arch/mips/mach-pic32/Kconfig |  20 +
>  arch/mips/mach-pic32/Makefile|   7 ++
>  arch/mips/mach-pic32/config.mk   |   8 ++
>  arch/mips/mach-pic32/cpu.c   |  13 +++
>  8 files changed, 230 insertions(+)
>  create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
>  create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
>  create mode 100644 arch/mips/mach-pic32/Kconfig
>  create mode 100644 arch/mips/mach-pic32/Makefile
>  create mode 100644 arch/mips/mach-pic32/config.mk
>  create mode 100644 arch/mips/mach-pic32/cpu.c
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 7f7e258..2a707e2 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -51,6 +51,10 @@ config TARGET_PB1X00
>  select SUPPORTS_CPU_MIPS32_R2
>  select SYS_MIPS_CACHE_INIT_RAM_LOAD
>  
> +config MACH_PIC32
> +bool "Support Microchip PIC32"
> +select OF_CONTROL
> +select DM
>  
>  endchoice
>  
> @@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
>  source "board/micronas/vct/Kconfig"
>  source "board/pb1x00/Kconfig"
>  source "board/qemu-mips/Kconfig"
> +source "arch/mips/mach-pic32/Kconfig"
>  
>  if MIPS
>  
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 43f0f5c..8b7c7e3 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
>  libs-y += arch/mips/lib/
>  
>  libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
> +libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/
> diff --git a/arch/mips/include/asm/arch-pic32/clock.h 
> b/arch/mips/include/asm/arch-pic32/clock.h
> new file mode 100644
> index 000..6a4270d
> --- /dev/null
> +++ b/arch/mips/include/asm/arch-pic32/clock.h
> @@ -0,0 +1,31 @@
> +/*
> + * (c) 2015 Purna Chandra Mandal purna.man...@microchip.com>
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + */
> +
> +#ifndef __PIC32_CLOCK_H_
> +#define __PIC32_CLOCK_H_
> +
> +/* clk */
> +enum {
> +BASECLK,
> +PLLCLK,
> +MPLL,
> +SYSCLK,
> +PB1CLK,
> +PB2CLK,
> +PB3CLK,
> +PB4CLK,
> +PB5CLK,
> +PB6CLK,
> +PB7CLK,
> +REF1CLK,
> +REF2CLK,
> +REF3CLK,
> +REF4CLK,
> +REF5CLK,
> +};
> +
> +#endif/* __PIC32_CLOCK_H_ */
> diff --git a/arch/mips/include/asm/arch-pic32/pic32.h 
> b/arch/mips/include/asm/arch-pic32/pic32.h
> new file mode 100644
> index 000..4f2084f
> --- /dev/null
> +++ b/arch/mips/include/asm/arch-pic32/pic32.h
> @@ -0,0 +1,145 @@
> +/*
> + * (c) 2015 Paul Thacker 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + */
> +
> +#ifndef __PIC32_REGS_H__
> +#define __PIC32_REGS_H__
> +
> +#define _CLR_OFFSET(0x4)
> +#define _SET_OFFSET(0x8)
> +#define _INV_OFFSET(0xc)
> +
> +/* System Configuration */
> +#define PIC32_CFG_BASE(x) 0xbf80

you should a base address as physical address as seen by the CPU (e.g.
0x1f80). The driver then does a remap to KSEG1. But if you use
device-tree, you should get base address and size of a register space
from there. Example:

void __iomem *base = (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE)

> +#define CFGCON(PIC32_CFG_BASE(x))
> +#define DEVID(PIC32_CFG_BASE(x) + 0x0020)
> +#define SYSKEY(PIC32_CFG_BASE(x) + 0x0030)
> +#define PMD1(PIC32_CFG_BASE(x) + 0x0040)
> +#define PMD7(PIC32_CFG_BASE(x) + 0x00a0)
> +#define CFGEBIA(PIC32_CFG_BASE(x) + 0x00c0)
> +#define CFGEBIC(PIC32_CFG_BASE(x) + 0x00d0)
> +#define CFGPG(PIC32_CFG_BASE(x) + 0x00e0)
> +#define CFGMPLL(PIC32_CFG_BASE(x) + 0x0100)

registers should only defined by their relative offset. The addition to
the base address is not needed. A driver could do:

readl(base + CFGCON)

> +
> +/* Clock & Reset */
> +#define RESET_BASE0xbf80
> +
> +/* Non Volatile Memory (NOR flash) */
> +#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
> +
> +/* Reset Control Registers */
> +#define RSWRST(RESET_BASE + 0x1250)
> +
> +/* Oscillator Configuration */
> +#define OSCCON(RESET_BASE + 0x1200)
> +#define SPLLCON(RESET_BASE + 0x1220)
> +#define REFO1CON(RESET_BASE + 0x1280)
> +#define REFO1TRIM(RESET_BASE + 0x1290)
> +#define PB1DIV(RESET_BASE + 0x1340)
> +
> +/* Peripheral PORTA-PORTK / PORT0-PORT9 */
> +enum {
> +PIC32_PORT_A = 0,
> +PIC32_PORT_B = 1,
> +PIC32_PORT_C = 2,
> +PIC32_PORT_D = 3,
> +PIC32_PORT_E = 4,
> +PIC32_PORT_F = 5,
> +PIC32_PORT_G = 6,
> +PIC32_PORT_H = 7,
> +PIC32_PORT_J = 8, /* no PORT_I */
> +PIC32_PORT_K = 9,
> 

[U-Boot] [PATCH v1 02/18] MIPS: initial infrastructure for Microchip PIC32 architecture.

[Purna Chandra Mandal]

Signed-off-by: Purna Chandra Mandal 
---

 arch/mips/Kconfig|   5 ++
 arch/mips/Makefile   |   1 +
 arch/mips/include/asm/arch-pic32/clock.h |  31 +++
 arch/mips/include/asm/arch-pic32/pic32.h | 145 +++
 arch/mips/mach-pic32/Kconfig |  20 +
 arch/mips/mach-pic32/Makefile|   7 ++
 arch/mips/mach-pic32/config.mk   |   8 ++
 arch/mips/mach-pic32/cpu.c   |  13 +++
 8 files changed, 230 insertions(+)
 create mode 100644 arch/mips/include/asm/arch-pic32/clock.h
 create mode 100644 arch/mips/include/asm/arch-pic32/pic32.h
 create mode 100644 arch/mips/mach-pic32/Kconfig
 create mode 100644 arch/mips/mach-pic32/Makefile
 create mode 100644 arch/mips/mach-pic32/config.mk
 create mode 100644 arch/mips/mach-pic32/cpu.c

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7f7e258..2a707e2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -51,6 +51,10 @@ config TARGET_PB1X00
 select SUPPORTS_CPU_MIPS32_R2
 select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config MACH_PIC32
+bool "Support Microchip PIC32"
+select OF_CONTROL
+select DM
 
 endchoice
 
@@ -59,6 +63,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 43f0f5c..8b7c7e3 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,3 +8,4 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+libs-$(CONFIG_MACH_PIC32) += arch/mips/mach-pic32/
diff --git a/arch/mips/include/asm/arch-pic32/clock.h 
b/arch/mips/include/asm/arch-pic32/clock.h
new file mode 100644
index 000..6a4270d
--- /dev/null
+++ b/arch/mips/include/asm/arch-pic32/clock.h
@@ -0,0 +1,31 @@
+/*
+ * (c) 2015 Purna Chandra Mandal purna.man...@microchip.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_CLOCK_H_
+#define __PIC32_CLOCK_H_
+
+/* clk */
+enum {
+BASECLK,
+PLLCLK,
+MPLL,
+SYSCLK,
+PB1CLK,
+PB2CLK,
+PB3CLK,
+PB4CLK,
+PB5CLK,
+PB6CLK,
+PB7CLK,
+REF1CLK,
+REF2CLK,
+REF3CLK,
+REF4CLK,
+REF5CLK,
+};
+
+#endif/* __PIC32_CLOCK_H_ */
diff --git a/arch/mips/include/asm/arch-pic32/pic32.h 
b/arch/mips/include/asm/arch-pic32/pic32.h
new file mode 100644
index 000..4f2084f
--- /dev/null
+++ b/arch/mips/include/asm/arch-pic32/pic32.h
@@ -0,0 +1,145 @@
+/*
+ * (c) 2015 Paul Thacker 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#define _CLR_OFFSET(0x4)
+#define _SET_OFFSET(0x8)
+#define _INV_OFFSET(0xc)
+
+/* System Configuration */
+#define PIC32_CFG_BASE(x) 0xbf80
+#define CFGCON(PIC32_CFG_BASE(x))
+#define DEVID(PIC32_CFG_BASE(x) + 0x0020)
+#define SYSKEY(PIC32_CFG_BASE(x) + 0x0030)
+#define PMD1(PIC32_CFG_BASE(x) + 0x0040)
+#define PMD7(PIC32_CFG_BASE(x) + 0x00a0)
+#define CFGEBIA(PIC32_CFG_BASE(x) + 0x00c0)
+#define CFGEBIC(PIC32_CFG_BASE(x) + 0x00d0)
+#define CFGPG(PIC32_CFG_BASE(x) + 0x00e0)
+#define CFGMPLL(PIC32_CFG_BASE(x) + 0x0100)
+
+/* Clock & Reset */
+#define RESET_BASE0xbf80
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE  (RESET_BASE + 0x0600)
+
+/* Reset Control Registers */
+#define RSWRST(RESET_BASE + 0x1250)
+
+/* Oscillator Configuration */
+#define OSCCON(RESET_BASE + 0x1200)
+#define SPLLCON(RESET_BASE + 0x1220)
+#define REFO1CON(RESET_BASE + 0x1280)
+#define REFO1TRIM(RESET_BASE + 0x1290)
+#define PB1DIV(RESET_BASE + 0x1340)
+
+/* Peripheral PORTA-PORTK / PORT0-PORT9 */
+enum {
+PIC32_PORT_A = 0,
+PIC32_PORT_B = 1,
+PIC32_PORT_C = 2,
+PIC32_PORT_D = 3,
+PIC32_PORT_E = 4,
+PIC32_PORT_F = 5,
+PIC32_PORT_G = 6,
+PIC32_PORT_H = 7,
+PIC32_PORT_J = 8, /* no PORT_I */
+PIC32_PORT_K = 9,
+PIC32_PORT_MAX
+};
+
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE0xbf80
+#define U1RXR(PPS_IN_BASE + 0x1468)
+#define U2RXR(PPS_IN_BASE + 0x1470)
+#define SDI1R(PPS_IN_BASE + 0x149c)
+#define SDI2R(PPS_IN_BASE + 0x14a8)
+
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE0xbf801500
+#define PPS_OUT(prt, pi)(PPS_OUT_BASE + prt) * 16) + (pi)) << 2))
+#define RPA14RPPS_OUT(PIC32_PORT_A, 14)
+#define RPB0RPPS_OUT(PIC32_PORT_B, 0)
+#define RPB14RPPS_OUT(PIC32_PORT_B, 14)
+#define RPD0RPPS_OUT(PIC32_PORT_D, 0)
+#define RPD3RPPS_OUT(PIC32_PORT_D, 3)
+#define RPG8RPPS_OUT(PIC32_PORT_G, 8)
+#define RPG9RPPS_OUT(PIC32_PORT_G, 9)
+
+/* Peripheral Pin Control */
+#define