Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Mon, May 6, 2019 at 5:36 AM Chee, Tien Fong wrote:
>
> On Fri, 2019-05-03 at 13:26 +0200, Simon Goldschmidt wrote:
> > On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong > com> wrote:
> > >
> > >
> > > On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > > >
> > > > On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> > > > wrote:
> > > > >
> > > > >
> > > > >
> > > > > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > From: Tien Fong Chee
> > > > > > >
> > > > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > > > loading
> > > > > > > from
> > > > > > > filesystem. The driver are designed based on generic
> > > > > > > firmware
> > > > > > > loader
> > > > > > > framework. The driver can handle FPGA program operation
> > > > > > > from
> > > > > > > loading FPGA
> > > > > > > bitstream in flash to memory and then to program FPGA.
> > > > > > >
> > > > > > > Signed-off-by: Tien Fong Chee
> > > > > > >
> > > > > > > ---
> > > > > > >
> > > > > > > changes for v12
> > > > > > > - No changes.
> > > > > > >
> > > > > > > changes for v11
> > > > > > > - No changes.
> > > > > > >
> > > > > > > changes for v10
> > > > > > > -Cleaned up the codes.
> > > > > > > -Return -EPERM when programing core on non early IO release
> > > > > > > mode. >
> > > > > > > -Using live function to get rid of gd->
> > > > > > You got rid of gd-> in v10? How come I see numerous
> > > > > > references to
> > > > > > it
> > > > > > below?
> > > > > get rid of using gd->fdt_blob for finding the node_offset.
> > > > > Details in https://patchwork.ozlabs.org/patch/1044415/
> > > > Ah, ok. But still, here you're introducing yet more references to
> > > > gd-
> > > > >
> > > > > fdt_blob.
> > > > That wouldn't work with a live tree, either, or would it?
> > > Yeah, few direct call to config_pin function are still using gd-
> > > fdt_blob as argument. But, i'm not sure i should fix this function
> > > in
> > > this series patch set, or separately patch after this series patch
> > > set?
> > >
> > > What do you think?
> > While I do have a strong opinion that this should be cleaned up,
> > it would be kind of off-topic in this patch. I was just confused by
> > the
> > version log.
> >
> > Regards,
> > Simon
> Okay, how about we keep these changes. I will send out the fix
> separately after this patch set.
That would be best, I think, yes.
Regards,
Simon
>
> Thanks.
> >
> > >
> > >
> > > Thanks,
> > > TF
> > > >
> > > >
> > > > >
> > > > >
> > > > >
> > > > > -/*
> > > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > > used by
> > > > > FPGA driver.
> > > > > - * Return 0 for sucess, non-zero for error.
> > > > > - */
> > > > > +ofnode get_fpga_mgr_ofnode(void)
> > > > > +{
> > > > > + int node_offset;
> > > > > +
> > > > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > > > >
> > > > > nit: using of live functions would be better to get rid of gd-
> > > > > >.
> > > > >
> > > > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > > > + _offset, 1);
> > > > >
> > > > > Thanks.
> > > > > >
> > > > > >
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > -Removed @0 for fs-loader node
> > > > > > >
> > > > > > > changes for v9
> > > > > > > - Support data offset
> > > > > > > - Added default DDR load address
> > > > > > > - Squashed the image.h
> > > > > > > - Changed to phandle
> > > > > > > - Ensure the DDR is fully up running by checking the gd-
> > > > > > > >ram
> > > > > > >
> > > > > > > changes for v8
> > > > > > > - Added codes to discern bitstream type based on fpga node
> > > > > > > name.
> > > > > > >
> > > > > > > changes for v7
> > > > > > > - Restructure the FPGA driver to support both peripheral
> > > > > > > bitstream
> > > > > > > and core
> > > > > > >bitstream bundled into FIT image.
> > > > > > > - Support loadable property for core bitstream. User can
> > > > > > > set
> > > > > > > loadable
> > > > > > >in DDR for better performance. This loading would be
> > > > > > > done in
> > > > > > > one
> > > > > > > large
> > > > > > >chunk instead of chunk by chunk loading with small
> > > > > > > memory
> > > > > > > buffer.
> > > > > > > ---
> > > > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17
> > > > > > > +
> > > > > > > .../include/mach/fpga_manager_arria10.h| 39
> > > > > > > +-
> > > > > > > drivers/fpga/socfpga_arria10.c | 497
> > > > > > > -
> > > > > > > include/image.h| 4
> > > > > > > +
> > > > > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > > > > >
> > > > > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > >
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Fri, 2019-05-03 at 13:26 +0200, Simon Goldschmidt wrote:
> On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong com> wrote:
> >
> >
> > On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > >
> > > On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> > > wrote:
> > > >
> > > >
> > > >
> > > > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > > > >
> > > > >
> > > > >
> > > > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee
> > > > > >
> > > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > > loading
> > > > > > from
> > > > > > filesystem. The driver are designed based on generic
> > > > > > firmware
> > > > > > loader
> > > > > > framework. The driver can handle FPGA program operation
> > > > > > from
> > > > > > loading FPGA
> > > > > > bitstream in flash to memory and then to program FPGA.
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee
> > > > > >
> > > > > > ---
> > > > > >
> > > > > > changes for v12
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v11
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v10
> > > > > > -Cleaned up the codes.
> > > > > > -Return -EPERM when programing core on non early IO release
> > > > > > mode. >
> > > > > > -Using live function to get rid of gd->
> > > > > You got rid of gd-> in v10? How come I see numerous
> > > > > references to
> > > > > it
> > > > > below?
> > > > get rid of using gd->fdt_blob for finding the node_offset.
> > > > Details in https://patchwork.ozlabs.org/patch/1044415/
> > > Ah, ok. But still, here you're introducing yet more references to
> > > gd-
> > > >
> > > > fdt_blob.
> > > That wouldn't work with a live tree, either, or would it?
> > Yeah, few direct call to config_pin function are still using gd-
> > fdt_blob as argument. But, i'm not sure i should fix this function
> > in
> > this series patch set, or separately patch after this series patch
> > set?
> >
> > What do you think?
> While I do have a strong opinion that this should be cleaned up,
> it would be kind of off-topic in this patch. I was just confused by
> the
> version log.
>
> Regards,
> Simon
Okay, how about we keep these changes. I will send out the fix
separately after this patch set.
Thanks.
>
> >
> >
> > Thanks,
> > TF
> > >
> > >
> > > >
> > > >
> > > >
> > > > -/*
> > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > used by
> > > > FPGA driver.
> > > > - * Return 0 for sucess, non-zero for error.
> > > > - */
> > > > +ofnode get_fpga_mgr_ofnode(void)
> > > > +{
> > > > + int node_offset;
> > > > +
> > > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > > >
> > > > nit: using of live functions would be better to get rid of gd-
> > > > >.
> > > >
> > > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > > + _offset, 1);
> > > >
> > > > Thanks.
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > -Removed @0 for fs-loader node
> > > > > >
> > > > > > changes for v9
> > > > > > - Support data offset
> > > > > > - Added default DDR load address
> > > > > > - Squashed the image.h
> > > > > > - Changed to phandle
> > > > > > - Ensure the DDR is fully up running by checking the gd-
> > > > > > >ram
> > > > > >
> > > > > > changes for v8
> > > > > > - Added codes to discern bitstream type based on fpga node
> > > > > > name.
> > > > > >
> > > > > > changes for v7
> > > > > > - Restructure the FPGA driver to support both peripheral
> > > > > > bitstream
> > > > > > and core
> > > > > > bitstream bundled into FIT image.
> > > > > > - Support loadable property for core bitstream. User can
> > > > > > set
> > > > > > loadable
> > > > > > in DDR for better performance. This loading would be
> > > > > > done in
> > > > > > one
> > > > > > large
> > > > > > chunk instead of chunk by chunk loading with small
> > > > > > memory
> > > > > > buffer.
> > > > > > ---
> > > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17
> > > > > > +
> > > > > > .../include/mach/fpga_manager_arria10.h| 39
> > > > > > +-
> > > > > > drivers/fpga/socfpga_arria10.c | 497
> > > > > > -
> > > > > > include/image.h| 4
> > > > > > +
> > > > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > index 998d811210..cc761967c7 100644
> > > > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > @@ -18,6 +18,23 @@
> > > > > > /dts-v1/;
> > > > > > #include "socfpga_arria10_socdk.dtsi"
> > > > > >
> > > > > > +/ {
> > > > > > + chosen {
> > > > > > +
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong wrote:
>
> On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> > wrote:
> > >
> > >
> > > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > > >
> > > >
> > > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> > > > >
> > > > >
> > > > > From: Tien Fong Chee
> > > > >
> > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > loading
> > > > > from
> > > > > filesystem. The driver are designed based on generic firmware
> > > > > loader
> > > > > framework. The driver can handle FPGA program operation from
> > > > > loading FPGA
> > > > > bitstream in flash to memory and then to program FPGA.
> > > > >
> > > > > Signed-off-by: Tien Fong Chee
> > > > >
> > > > > ---
> > > > >
> > > > > changes for v12
> > > > > - No changes.
> > > > >
> > > > > changes for v11
> > > > > - No changes.
> > > > >
> > > > > changes for v10
> > > > > -Cleaned up the codes.
> > > > > -Return -EPERM when programing core on non early IO release
> > > > > mode. >
> > > > > -Using live function to get rid of gd->
> > > > You got rid of gd-> in v10? How come I see numerous references to
> > > > it
> > > > below?
> > > get rid of using gd->fdt_blob for finding the node_offset.
> > > Details in https://patchwork.ozlabs.org/patch/1044415/
> > Ah, ok. But still, here you're introducing yet more references to gd-
> > >fdt_blob.
> > That wouldn't work with a live tree, either, or would it?
>
> Yeah, few direct call to config_pin function are still using gd-
> fdt_blob as argument. But, i'm not sure i should fix this function in
> this series patch set, or separately patch after this series patch set?
>
> What do you think?
While I do have a strong opinion that this should be cleaned up,
it would be kind of off-topic in this patch. I was just confused by the
version log.
Regards,
Simon
>
> Thanks,
> TF
> >
> > >
> > >
> > > -/*
> > > - * FPGA Manager to program the FPGA. This is the interface used by
> > > FPGA driver.
> > > - * Return 0 for sucess, non-zero for error.
> > > - */
> > > +ofnode get_fpga_mgr_ofnode(void)
> > > +{
> > > + int node_offset;
> > > +
> > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > >
> > > nit: using of live functions would be better to get rid of gd->.
> > >
> > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > + _offset, 1);
> > >
> > > Thanks.
> > > >
> > > >
> > > > >
> > > > >
> > > > > -Removed @0 for fs-loader node
> > > > >
> > > > > changes for v9
> > > > > - Support data offset
> > > > > - Added default DDR load address
> > > > > - Squashed the image.h
> > > > > - Changed to phandle
> > > > > - Ensure the DDR is fully up running by checking the gd->ram
> > > > >
> > > > > changes for v8
> > > > > - Added codes to discern bitstream type based on fpga node
> > > > > name.
> > > > >
> > > > > changes for v7
> > > > > - Restructure the FPGA driver to support both peripheral
> > > > > bitstream
> > > > > and core
> > > > >bitstream bundled into FIT image.
> > > > > - Support loadable property for core bitstream. User can set
> > > > > loadable
> > > > >in DDR for better performance. This loading would be done in
> > > > > one
> > > > > large
> > > > >chunk instead of chunk by chunk loading with small memory
> > > > > buffer.
> > > > > ---
> > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > > .../include/mach/fpga_manager_arria10.h| 39 +-
> > > > > drivers/fpga/socfpga_arria10.c | 497
> > > > > -
> > > > > include/image.h| 4 +
> > > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > index 998d811210..cc761967c7 100644
> > > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > @@ -18,6 +18,23 @@
> > > > > /dts-v1/;
> > > > > #include "socfpga_arria10_socdk.dtsi"
> > > > >
> > > > > +/ {
> > > > > + chosen {
> > > > > + firmware-loader = <_loader0>;
> > > > > + };
> > > > > +
> > > > > + fs_loader0: fs-loader {
> > > > > + u-boot,dm-pre-reloc;
> > > > > + compatible = "u-boot,fs-loader";
> > > > > + phandlepart = < 1>;
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +_mgr {
> > > > > + u-boot,dm-pre-reloc;
> > > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > > +};
> > > > > +
> > > > >{
> > > > > u-boot,dm-pre-reloc;
> > > > > status = "okay";
> > > > > diff --git a/arch/arm/mach-
> > > > > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > index 09d13f6fd3..c5f67714aa 100644
> > > > >
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> wrote:
> >
> >
> > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > loading
> > > > from
> > > > filesystem. The driver are designed based on generic firmware
> > > > loader
> > > > framework. The driver can handle FPGA program operation from
> > > > loading FPGA
> > > > bitstream in flash to memory and then to program FPGA.
> > > >
> > > > Signed-off-by: Tien Fong Chee
> > > >
> > > > ---
> > > >
> > > > changes for v12
> > > > - No changes.
> > > >
> > > > changes for v11
> > > > - No changes.
> > > >
> > > > changes for v10
> > > > -Cleaned up the codes.
> > > > -Return -EPERM when programing core on non early IO release
> > > > mode. >
> > > > -Using live function to get rid of gd->
> > > You got rid of gd-> in v10? How come I see numerous references to
> > > it
> > > below?
> > get rid of using gd->fdt_blob for finding the node_offset.
> > Details in https://patchwork.ozlabs.org/patch/1044415/
> Ah, ok. But still, here you're introducing yet more references to gd-
> >fdt_blob.
> That wouldn't work with a live tree, either, or would it?
Yeah, few direct call to config_pin function are still using gd-
fdt_blob as argument. But, i'm not sure i should fix this function in
this series patch set, or separately patch after this series patch set?
What do you think?
Thanks,
TF
>
> >
> >
> > -/*
> > - * FPGA Manager to program the FPGA. This is the interface used by
> > FPGA driver.
> > - * Return 0 for sucess, non-zero for error.
> > - */
> > +ofnode get_fpga_mgr_ofnode(void)
> > +{
> > + int node_offset;
> > +
> > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> >
> > nit: using of live functions would be better to get rid of gd->.
> >
> > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > + _offset, 1);
> >
> > Thanks.
> > >
> > >
> > > >
> > > >
> > > > -Removed @0 for fs-loader node
> > > >
> > > > changes for v9
> > > > - Support data offset
> > > > - Added default DDR load address
> > > > - Squashed the image.h
> > > > - Changed to phandle
> > > > - Ensure the DDR is fully up running by checking the gd->ram
> > > >
> > > > changes for v8
> > > > - Added codes to discern bitstream type based on fpga node
> > > > name.
> > > >
> > > > changes for v7
> > > > - Restructure the FPGA driver to support both peripheral
> > > > bitstream
> > > > and core
> > > > bitstream bundled into FIT image.
> > > > - Support loadable property for core bitstream. User can set
> > > > loadable
> > > > in DDR for better performance. This loading would be done in
> > > > one
> > > > large
> > > > chunk instead of chunk by chunk loading with small memory
> > > > buffer.
> > > > ---
> > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > .../include/mach/fpga_manager_arria10.h| 39 +-
> > > > drivers/fpga/socfpga_arria10.c | 497
> > > > -
> > > > include/image.h| 4 +
> > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > index 998d811210..cc761967c7 100644
> > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > @@ -18,6 +18,23 @@
> > > > /dts-v1/;
> > > > #include "socfpga_arria10_socdk.dtsi"
> > > >
> > > > +/ {
> > > > + chosen {
> > > > + firmware-loader = <_loader0>;
> > > > + };
> > > > +
> > > > + fs_loader0: fs-loader {
> > > > + u-boot,dm-pre-reloc;
> > > > + compatible = "u-boot,fs-loader";
> > > > + phandlepart = < 1>;
> > > > + };
> > > > +};
> > > > +
> > > > +_mgr {
> > > > + u-boot,dm-pre-reloc;
> > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > +};
> > > > +
> > > > {
> > > > u-boot,dm-pre-reloc;
> > > > status = "okay";
> > > > diff --git a/arch/arm/mach-
> > > > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > index 09d13f6fd3..c5f67714aa 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > @@ -1,9 +1,13 @@
> > > > /* SPDX-License-Identifier: GPL-2.0 */
> > > > /*
> > > > - * Copyright (C) 2017 Intel Corporation
> > > > + * Copyright (C) 2017-2019 Intel Corporation
> > > > * All rights reserved.
> > > > */
> > > >
> > > > +#include
> > > > +#include
> > > > +#include
> > > > +
> > > > #ifndef
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
wrote:
>
> On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> >
> > On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> > >
> > > From: Tien Fong Chee
> > >
> > > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > > from
> > > filesystem. The driver are designed based on generic firmware
> > > loader
> > > framework. The driver can handle FPGA program operation from
> > > loading FPGA
> > > bitstream in flash to memory and then to program FPGA.
> > >
> > > Signed-off-by: Tien Fong Chee
> > >
> > > ---
> > >
> > > changes for v12
> > > - No changes.
> > >
> > > changes for v11
> > > - No changes.
> > >
> > > changes for v10
> > > -Cleaned up the codes.
> > > -Return -EPERM when programing core on non early IO release mode. >
> > > -Using live function to get rid of gd->
> > You got rid of gd-> in v10? How come I see numerous references to it
> > below?
>
> get rid of using gd->fdt_blob for finding the node_offset.
> Details in https://patchwork.ozlabs.org/patch/1044415/
Ah, ok. But still, here you're introducing yet more references to gd->fdt_blob.
That wouldn't work with a live tree, either, or would it?
Regards,
Simon
>
> -/*
> - * FPGA Manager to program the FPGA. This is the interface used by
> FPGA driver.
> - * Return 0 for sucess, non-zero for error.
> - */
> +ofnode get_fpga_mgr_ofnode(void)
> +{
> + int node_offset;
> +
> + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
>
> nit: using of live functions would be better to get rid of gd->.
>
> + COMPAT_ALTERA_SOCFPGA_FPGA0,
> + _offset, 1);
>
> Thanks.
> >
> > >
> > > -Removed @0 for fs-loader node
> > >
> > > changes for v9
> > > - Support data offset
> > > - Added default DDR load address
> > > - Squashed the image.h
> > > - Changed to phandle
> > > - Ensure the DDR is fully up running by checking the gd->ram
> > >
> > > changes for v8
> > > - Added codes to discern bitstream type based on fpga node name.
> > >
> > > changes for v7
> > > - Restructure the FPGA driver to support both peripheral bitstream
> > > and core
> > >bitstream bundled into FIT image.
> > > - Support loadable property for core bitstream. User can set
> > > loadable
> > >in DDR for better performance. This loading would be done in one
> > > large
> > >chunk instead of chunk by chunk loading with small memory
> > > buffer.
> > > ---
> > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > .../include/mach/fpga_manager_arria10.h| 39 +-
> > > drivers/fpga/socfpga_arria10.c | 497
> > > -
> > > include/image.h| 4 +
> > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > index 998d811210..cc761967c7 100644
> > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > @@ -18,6 +18,23 @@
> > > /dts-v1/;
> > > #include "socfpga_arria10_socdk.dtsi"
> > >
> > > +/ {
> > > + chosen {
> > > + firmware-loader = <_loader0>;
> > > + };
> > > +
> > > + fs_loader0: fs-loader {
> > > + u-boot,dm-pre-reloc;
> > > + compatible = "u-boot,fs-loader";
> > > + phandlepart = < 1>;
> > > + };
> > > +};
> > > +
> > > +_mgr {
> > > + u-boot,dm-pre-reloc;
> > > + altr,bitstream = "fit_spl_fpga.itb";
> > > +};
> > > +
> > >{
> > > u-boot,dm-pre-reloc;
> > > status = "okay";
> > > diff --git a/arch/arm/mach-
> > > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > > socfpga/include/mach/fpga_manager_arria10.h
> > > index 09d13f6fd3..c5f67714aa 100644
> > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > @@ -1,9 +1,13 @@
> > > /* SPDX-License-Identifier: GPL-2.0 */
> > > /*
> > > - * Copyright (C) 2017 Intel Corporation
> > > + * Copyright (C) 2017-2019 Intel Corporation
> > >* All rights reserved.
> > >*/
> > >
> > > +#include
> > > +#include
> > > +#include
> > > +
> > > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > #define _FPGA_MANAGER_ARRIA10_H_
> > >
> > > @@ -51,6 +55,10 @@
> > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > > BIT(24)
> > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > > 16
> > >
> > > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > > +#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
> > > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > > #ifndef __ASSEMBLY__
> > >
> > > struct socfpga_fpga_manager {
> > > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > > u32 imgcfg_fifo_status;
> > > };
> > >
> > > +enum
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> > loader
> > framework. The driver can handle FPGA program operation from
> > loading FPGA
> > bitstream in flash to memory and then to program FPGA.
> >
> > Signed-off-by: Tien Fong Chee
> >
> > ---
> >
> > changes for v12
> > - No changes.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > -Cleaned up the codes.
> > -Return -EPERM when programing core on non early IO release mode. >
> > -Using live function to get rid of gd->
> You got rid of gd-> in v10? How come I see numerous references to it
> below?
get rid of using gd->fdt_blob for finding the node_offset.
Details in https://patchwork.ozlabs.org/patch/1044415/
-/*
- * FPGA Manager to program the FPGA. This is the interface used by
FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
+ofnode get_fpga_mgr_ofnode(void)
+{
+ int node_offset;
+
+ fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
nit: using of live functions would be better to get rid of gd->.
+ COMPAT_ALTERA_SOCFPGA_FPGA0,
+ _offset, 1);
Thanks.
>
> >
> > -Removed @0 for fs-loader node
> >
> > changes for v9
> > - Support data offset
> > - Added default DDR load address
> > - Squashed the image.h
> > - Changed to phandle
> > - Ensure the DDR is fully up running by checking the gd->ram
> >
> > changes for v8
> > - Added codes to discern bitstream type based on fpga node name.
> >
> > changes for v7
> > - Restructure the FPGA driver to support both peripheral bitstream
> > and core
> > bitstream bundled into FIT image.
> > - Support loadable property for core bitstream. User can set
> > loadable
> > in DDR for better performance. This loading would be done in one
> > large
> > chunk instead of chunk by chunk loading with small memory
> > buffer.
> > ---
> > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > .../include/mach/fpga_manager_arria10.h| 39 +-
> > drivers/fpga/socfpga_arria10.c | 497
> > -
> > include/image.h| 4 +
> > 4 files changed, 542 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > index 998d811210..cc761967c7 100644
> > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > @@ -18,6 +18,23 @@
> > /dts-v1/;
> > #include "socfpga_arria10_socdk.dtsi"
> >
> > +/ {
> > + chosen {
> > + firmware-loader = <_loader0>;
> > + };
> > +
> > + fs_loader0: fs-loader {
> > + u-boot,dm-pre-reloc;
> > + compatible = "u-boot,fs-loader";
> > + phandlepart = < 1>;
> > + };
> > +};
> > +
> > +_mgr {
> > + u-boot,dm-pre-reloc;
> > + altr,bitstream = "fit_spl_fpga.itb";
> > +};
> > +
> > {
> > u-boot,dm-pre-reloc;
> > status = "okay";
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h
> > index 09d13f6fd3..c5f67714aa 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > @@ -1,9 +1,13 @@
> > /* SPDX-License-Identifier: GPL-2.0 */
> > /*
> > - * Copyright (C) 2017 Intel Corporation
> > + * Copyright (C) 2017-2019 Intel Corporation
> > * All rights reserved.
> > */
> >
> > +#include
> > +#include
> > +#include
> > +
> > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > #define _FPGA_MANAGER_ARRIA10_H_
> >
> > @@ -51,6 +55,10 @@
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > BIT(24)
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > 16
> >
> > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > +#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
> > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > #ifndef __ASSEMBLY__
> >
> > struct socfpga_fpga_manager {
> > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > u32 imgcfg_fifo_status;
> > };
> >
> > +enum rbf_type {
> > + unknown,
> > + periph_section,
> > + core_section
> > +};
> > +
> > +enum rbf_security {
> > + invalid,
> > + unencrypted,
> > + encrypted
> > +};
> > +
> > +struct rbf_info {
> > + enum rbf_type section;
> > + enum rbf_security security;
> > +};
> > +
> > +struct fpga_loadfs_info {
> > + fpga_fs_info *fpga_fsinfo;
> > + u32 remaining;
> > + u32 offset;
> > + struct rbf_info rbfinfo;
> > +};
> > +
> >
Re: [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
On 19.03.19 09:50, tien.fong.c...@intel.com wrote:
From: Tien Fong Chee
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
-Cleaned up the codes.
-Return -EPERM when programing core on non early IO release mode. > -Using live
function to get rid of gd->
You got rid of gd-> in v10? How come I see numerous references to it below?
Regards,
Simon
-Removed @0 for fs-loader node
changes for v9
- Support data offset
- Added default DDR load address
- Squashed the image.h
- Changed to phandle
- Ensure the DDR is fully up running by checking the gd->ram
changes for v8
- Added codes to discern bitstream type based on fpga node name.
changes for v7
- Restructure the FPGA driver to support both peripheral bitstream and core
bitstream bundled into FIT image.
- Support loadable property for core bitstream. User can set loadable
in DDR for better performance. This loading would be done in one large
chunk instead of chunk by chunk loading with small memory buffer.
---
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
.../include/mach/fpga_manager_arria10.h| 39 +-
drivers/fpga/socfpga_arria10.c | 497 -
include/image.h| 4 +
4 files changed, 542 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 998d811210..cc761967c7 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -18,6 +18,23 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
+/ {
+ chosen {
+ firmware-loader = <_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = < 1>;
+ };
+};
+
+_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fit_spl_fpga.itb";
+};
+
{
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 09d13f6fd3..c5f67714aa 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -1,9 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2017 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
* All rights reserved.
*/
+#include
+#include
+#include
+
#ifndef _FPGA_MANAGER_ARRIA10_H_
#define _FPGA_MANAGER_ARRIA10_H_
@@ -51,6 +55,10 @@
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSKBIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
@@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
u32 imgcfg_fifo_status;
};
+enum rbf_type {
+ unknown,
+ periph_section,
+ core_section
+};
+
+enum rbf_security {
+ invalid,
+ unencrypted,
+ encrypted
+};
+
+struct rbf_info {
+ enum rbf_type section;
+ enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+ fpga_fs_info *fpga_fsinfo;
+ u32 remaining;
+ u32 offset;
+ struct rbf_info rbfinfo;
+};
+
/* Functions */
int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
-
+const char *get_fpga_filename(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9499d1a014..9df2c430d7 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
*/
-
#include
#include
#include
@@ -10,8 +9,11 @@
#include
#include
#include
+#include
#include
+#include
#include
+#include
#include
#include
@@ -21,6 +23,9 @@
#define COMPRESSION_OFFSET229
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
[U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
From: Tien Fong Chee
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
-Cleaned up the codes.
-Return -EPERM when programing core on non early IO release mode.
-Using live function to get rid of gd->
-Removed @0 for fs-loader node
changes for v9
- Support data offset
- Added default DDR load address
- Squashed the image.h
- Changed to phandle
- Ensure the DDR is fully up running by checking the gd->ram
changes for v8
- Added codes to discern bitstream type based on fpga node name.
changes for v7
- Restructure the FPGA driver to support both peripheral bitstream and core
bitstream bundled into FIT image.
- Support loadable property for core bitstream. User can set loadable
in DDR for better performance. This loading would be done in one large
chunk instead of chunk by chunk loading with small memory buffer.
---
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
.../include/mach/fpga_manager_arria10.h| 39 +-
drivers/fpga/socfpga_arria10.c | 497 -
include/image.h| 4 +
4 files changed, 542 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 998d811210..cc761967c7 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -18,6 +18,23 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
+/ {
+ chosen {
+ firmware-loader = <_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = < 1>;
+ };
+};
+
+_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fit_spl_fpga.itb";
+};
+
{
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 09d13f6fd3..c5f67714aa 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -1,9 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2017 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
* All rights reserved.
*/
+#include
+#include
+#include
+
#ifndef _FPGA_MANAGER_ARRIA10_H_
#define _FPGA_MANAGER_ARRIA10_H_
@@ -51,6 +55,10 @@
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
@@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
u32 imgcfg_fifo_status;
};
+enum rbf_type {
+ unknown,
+ periph_section,
+ core_section
+};
+
+enum rbf_security {
+ invalid,
+ unencrypted,
+ encrypted
+};
+
+struct rbf_info {
+ enum rbf_type section;
+ enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+ fpga_fs_info *fpga_fsinfo;
+ u32 remaining;
+ u32 offset;
+ struct rbf_info rbfinfo;
+};
+
/* Functions */
int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
-
+const char *get_fpga_filename(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9499d1a014..9df2c430d7 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017 Intel Corporation
+ * Copyright (C) 2017-2019 Intel Corporation
*/
-
#include
#include
#include
@@ -10,8 +9,11 @@
#include
#include
#include
+#include
#include
+#include
#include
+#include
#include
#include
@@ -21,6 +23,9 @@
#define COMPRESSION_OFFSET 229
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x100
+#define DEFAULT_DDR_LOAD_ADDRESS 0x400
+
+DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_fpga_manager *fpga_manager_base =
(void
