Re: [U-Boot] [PATCH v2] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

2017-09-25 Thread Jagan Teki 
On Thu, Aug 31, 2017 at 7:43 PM, Jagan Teki  wrote:
> On Thu, Aug 31, 2017 at 10:26 AM, Yogesh Gaur
>  wrote:
>> Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
>>
>> The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
>> dual and quad. Supports subsector erase with 4KB granularity, have support
>> of FSR(flag status register) and flash size is 64MB.
>>
>> Signed-off-by: Yogesh Gaur 
>
> Reviewed-by: Jagan Teki 

Applied to u-boot-spi/master

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH v2] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

2017-08-31 Thread Jagan Teki 
On Thu, Aug 31, 2017 at 10:26 AM, Yogesh Gaur
 wrote:
> Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
>
> The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
> dual and quad. Supports subsector erase with 4KB granularity, have support
> of FSR(flag status register) and flash size is 64MB.
>
> Signed-off-by: Yogesh Gaur 

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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[U-Boot] [PATCH v2] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

2017-08-31 Thread Yogesh Gaur 
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.

The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.

Signed-off-by: Yogesh Gaur 
---
Change in v2:
 - Incorporated Jagan's review comments. Removed macro SPI_FLASH_CFI_MFR_MICRON
---
 drivers/mtd/spi/spi_flash_ids.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index c4ccf48..e4f4570 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -134,6 +134,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"n25q1024a",  INFO(0x20bb21, 0x0,  64 * 1024,  2048, RD_FULL | 
WR_QPP | E_FSR | SECT_4K) },
{"mt25qu02g",  INFO(0x20bb22, 0x0,  64 * 1024,  4096, RD_FULL | 
WR_QPP | E_FSR | SECT_4K) },
{"mt25ql02g",  INFO(0x20ba22, 0x0,  64 * 1024,  4096, RD_FULL | 
WR_QPP | E_FSR | SECT_4K) },
+   {"mt35xu512g", INFO6(0x2c5b1a, 0x104100,  128 * 1024,  512, E_FSR | 
SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_SST/* SST */
{"sst25vf040b",INFO(0xbf258d, 0x0,  64 * 1024, 8, SECT_4K | 
SST_WR) },
-- 
1.9.1

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[U-Boot] [PATCH v2] mtd/spi: Add MT35XU512ABA1G12 NOR flash support

2017-08-30 Thread Yogesh Gaur 
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.

The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.

Signed-off-by: Yogesh Gaur 
---
Change in v2:
 - Incorporated Jagan's review comments. Removed macro SPI_FLASH_CFI_MFR_MICRON
---
 drivers/mtd/spi/spi_flash_ids.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index c4ccf48..e4f4570 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -134,6 +134,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"n25q1024a",  INFO(0x20bb21, 0x0,  64 * 1024,  2048, RD_FULL | 
WR_QPP | E_FSR | SECT_4K) },
{"mt25qu02g",  INFO(0x20bb22, 0x0,  64 * 1024,  4096, RD_FULL | 
WR_QPP | E_FSR | SECT_4K) },
{"mt25ql02g",  INFO(0x20ba22, 0x0,  64 * 1024,  4096, RD_FULL | 
WR_QPP | E_FSR | SECT_4K) },
+   {"mt35xu512g", INFO6(0x2c5b1a, 0x104100,  128 * 1024,  512, E_FSR | 
SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_SST/* SST */
{"sst25vf040b",INFO(0xbf258d, 0x0,  64 * 1024, 8, SECT_4K | 
SST_WR) },
-- 
1.9.1

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