Re: [U-Boot] [PATCH v2] net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541

2017-02-02 Thread Joe Hershberger 
On Fri, Dec 9, 2016 at 4:15 PM, John Haechten
 wrote:
> net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541
>
> Signed-off-by: John Haechten 

Acked-by: Joe Hershberger 
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[U-Boot] [PATCH v2] net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541

2016-12-09 Thread John Haechten 
net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541

Signed-off-by: John Haechten 
---

 drivers/net/phy/Makefile|   1 +
 drivers/net/phy/mscc.c  | 509 
 drivers/net/phy/phy.c   |   3 +
 include/config_phylib_all_drivers.h |   1 +
 include/configs/am335x_evm.h|   3 +
 include/phy.h   |   1 +
 6 files changed, 518 insertions(+)
 create mode 100644 drivers/net/phy/mscc.c

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 
1e299b9..d372971 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
 obj-$(CONFIG_PHY_TI) += ti.o
 obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
 obj-$(CONFIG_PHY_VITESSE) += vitesse.o
+obj-$(CONFIG_PHY_MSCC) += mscc.o
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c new file mode 
100644 index 000..e665b50
--- /dev/null
+++ b/drivers/net/phy/mscc.c
@@ -0,0 +1,509 @@
+/*
+ * Microsemi PHY drivers
+ *
+ * SPDX-License-Identifier: The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Microsemi Corporation
+ *
+ * Author: John Haechten
+ *
+ */
+
+#include 
+#include 
+
+/* Microsemi PHY ID's */
+#define PHY_ID_VSC8530  0x00070560
+#define PHY_ID_VSC8531  0x00070570
+#define PHY_ID_VSC8540  0x00070760
+#define PHY_ID_VSC8541  0x00070770
+
+/* Microsemi VSC85xx PHY Register Pages */
+#define MSCC_EXT_PAGE_ACCESS31 /* Page Access Register */
+#define MSCC_PHY_PAGE_STD  0x /* Standard registers */
+#define MSCC_PHY_PAGE_EXT1 0x0001 /* Extended registers - page 1 */
+#define MSCC_PHY_PAGE_EXT2 0x0002 /* Extended registers - page 2 */
+#define MSCC_PHY_PAGE_EXT3 0x0003 /* Extended registers - page 3 */
+#define MSCC_PHY_PAGE_EXT4 0x0004 /* Extended registers - page 4 */
+#define MSCC_PHY_PAGE_GPIO 0x0010 /* GPIO registers */
+#define MSCC_PHY_PAGE_TEST 0x2A30 /* TEST Page registers */
+#define MSCC_PHY_PAGE_TR   0x52B5 /* Token Ring Page registers */
+
+/* Std Page Register 28 - PHY AUX Control/Status */
+#define MIIM_AUX_CNTRL_STAT_REG28
+#define MIIM_AUX_CNTRL_STAT_ACTIPHY_TO (0x0004)
+#define MIIM_AUX_CNTRL_STAT_F_DUPLEX   (0x0020)
+#define MIIM_AUX_CNTRL_STAT_SPEED_MASK (0x0018)
+#define MIIM_AUX_CNTRL_STAT_SPEED_POS  (3)
+#define MIIM_AUX_CNTRL_STAT_SPEED_10M  (0x0)
+#define MIIM_AUX_CNTRL_STAT_SPEED_100M (0x1)
+#define MIIM_AUX_CNTRL_STAT_SPEED_1000M(0x2)
+
+/* Std Page Register 23 - Extended PHY CTRL_1 */
+#define MSCC_PHY_EXT_PHY_CNTL_1_REG23
+#define MAC_IF_SELECTION_MASK  (0x1800)
+#define MAC_IF_SELECTION_GMII  (0)
+#define MAC_IF_SELECTION_RMII  (1)
+#define MAC_IF_SELECTION_RGMII (2)
+#define MAC_IF_SELECTION_POS   (11)
+#define MAC_IF_SELECTION_WIDTH (2)
+
+/* Extended Page 2 Register 20E2 */
+#define MSCC_PHY_RGMII_CNTL_REG20
+#define VSC_FAST_LINK_FAIL2_ENA_MASK   (0x8000)
+#define RX_CLK_OUT_MASK(0x0800)
+#define RX_CLK_OUT_POS (11)
+#define RX_CLK_OUT_WIDTH   (1)
+#define RX_CLK_OUT_NORMAL  (0)
+#define RX_CLK_OUT_DISABLE (1)
+#define RGMII_RX_CLK_DELAY_POS (4)
+#define RGMII_RX_CLK_DELAY_WIDTH   (3)
+#define RGMII_RX_CLK_DELAY_MASK(0x0070)
+#define RGMII_TX_CLK_DELAY_POS (0)
+#define RGMII_TX_CLK_DELAY_WIDTH   (3)
+#define RGMII_TX_CLK_DELAY_MASK(0x0007)
+
+/* Extended Page 2 Register 27E2 */
+#define MSCC_PHY_WOL_MAC_CONTROL   27
+#define EDGE_RATE_CNTL_POS (5)
+#define EDGE_RATE_CNTL_WIDTH   (3)
+#define EDGE_RATE_CNTL_MASK(0x00E0)
+#define RMII_CLK_OUT_ENABLE_POS(4)
+#define RMII_CLK_OUT_ENABLE_WIDTH  (1)
+#define RMII_CLK_OUT_ENABLE_MASK   (0x10)
+
+/* Token Ring Page 0x52B5 Registers */
+#define MSCC_PHY_REG_TR_ADDR_1616
+#define MSCC_PHY_REG_TR_DATA_1717
+#define MSCC_PHY_REG_TR_DATA_1818
+
+/* Token Ring - Read Value in */
+#define MSCC_PHY_TR_16_READ(0xA000)
+/* Token Ring - Write Value out */
+#define MSCC_PHY_TR_16_WRITE   (0x8000)
+
+/* Token Ring Registers */
+#define MSCC_PHY_TR_LINKDETCTRL_POS(3)
+#define MSCC_PHY_TR_LINKDETCTRL_WIDTH  (2)
+#define MSCC_PHY_TR_LINKDETCTRL_VAL(3)
+#define MSCC_PHY_TR_LINKDETCTRL_MASK   (0x0018)
+#define MSCC_PHY_TR_LINKDETCTRL_ADDR   (0x07F8)
+
+#define MSCC_PHY_TR_VGATHRESH100_POS   (0)
+#define MSCC_PHY_TR_VGATHRESH100_WIDTH (7)
+#define MSCC_PHY_TR_VGATHRESH100_VAL   (0x0018)
+#define MSCC_PHY_TR_VGATHRESH100_MASK  (0x007f)
+#define MSCC_PHY_TR_VGATHRESH100_ADDR  (0x0FA4)
+
+#define MSCC_PHY_TR_VGAGAIN10_U_POS(0)
+#define MSCC_PHY_TR_VGAGAIN10_U_WIDTH

[U-Boot] [PATCH v2] net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541

2016-12-09 Thread John Haechten 
net:phy:MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541

Signed-off-by: John Haechten 
---

 drivers/net/phy/Makefile|   1 +
 drivers/net/phy/mscc.c  | 509 
 drivers/net/phy/phy.c   |   3 +
 include/config_phylib_all_drivers.h |   1 +
 include/configs/am335x_evm.h|   3 +
 include/phy.h   |   1 +
 6 files changed, 518 insertions(+)
 create mode 100644 drivers/net/phy/mscc.c

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 
1e299b9..d372971 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
 obj-$(CONFIG_PHY_TI) += ti.o
 obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
 obj-$(CONFIG_PHY_VITESSE) += vitesse.o
+obj-$(CONFIG_PHY_MSCC) += mscc.o
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c new file mode 
100644 index 000..e665b50
--- /dev/null
+++ b/drivers/net/phy/mscc.c
@@ -0,0 +1,509 @@
+/*
+ * Microsemi PHY drivers
+ *
+ * SPDX-License-Identifier: The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Microsemi Corporation
+ *
+ * Author: John Haechten
+ *
+ */
+
+#include 
+#include 
+
+/* Microsemi PHY ID's */
+#define PHY_ID_VSC8530  0x00070560
+#define PHY_ID_VSC8531  0x00070570
+#define PHY_ID_VSC8540  0x00070760
+#define PHY_ID_VSC8541  0x00070770
+
+/* Microsemi VSC85xx PHY Register Pages */
+#define MSCC_EXT_PAGE_ACCESS31 /* Page Access Register */
+#define MSCC_PHY_PAGE_STD  0x /* Standard registers */
+#define MSCC_PHY_PAGE_EXT1 0x0001 /* Extended registers - page 1 */
+#define MSCC_PHY_PAGE_EXT2 0x0002 /* Extended registers - page 2 */
+#define MSCC_PHY_PAGE_EXT3 0x0003 /* Extended registers - page 3 */
+#define MSCC_PHY_PAGE_EXT4 0x0004 /* Extended registers - page 4 */
+#define MSCC_PHY_PAGE_GPIO 0x0010 /* GPIO registers */
+#define MSCC_PHY_PAGE_TEST 0x2A30 /* TEST Page registers */
+#define MSCC_PHY_PAGE_TR   0x52B5 /* Token Ring Page registers */
+
+/* Std Page Register 28 - PHY AUX Control/Status */
+#define MIIM_AUX_CNTRL_STAT_REG28
+#define MIIM_AUX_CNTRL_STAT_ACTIPHY_TO (0x0004)
+#define MIIM_AUX_CNTRL_STAT_F_DUPLEX   (0x0020)
+#define MIIM_AUX_CNTRL_STAT_SPEED_MASK (0x0018)
+#define MIIM_AUX_CNTRL_STAT_SPEED_POS  (3)
+#define MIIM_AUX_CNTRL_STAT_SPEED_10M  (0x0)
+#define MIIM_AUX_CNTRL_STAT_SPEED_100M (0x1)
+#define MIIM_AUX_CNTRL_STAT_SPEED_1000M(0x2)
+
+/* Std Page Register 23 - Extended PHY CTRL_1 */
+#define MSCC_PHY_EXT_PHY_CNTL_1_REG23
+#define MAC_IF_SELECTION_MASK  (0x1800)
+#define MAC_IF_SELECTION_GMII  (0)
+#define MAC_IF_SELECTION_RMII  (1)
+#define MAC_IF_SELECTION_RGMII (2)
+#define MAC_IF_SELECTION_POS   (11)
+#define MAC_IF_SELECTION_WIDTH (2)
+
+/* Extended Page 2 Register 20E2 */
+#define MSCC_PHY_RGMII_CNTL_REG20
+#define VSC_FAST_LINK_FAIL2_ENA_MASK   (0x8000)
+#define RX_CLK_OUT_MASK(0x0800)
+#define RX_CLK_OUT_POS (11)
+#define RX_CLK_OUT_WIDTH   (1)
+#define RX_CLK_OUT_NORMAL  (0)
+#define RX_CLK_OUT_DISABLE (1)
+#define RGMII_RX_CLK_DELAY_POS (4)
+#define RGMII_RX_CLK_DELAY_WIDTH   (3)
+#define RGMII_RX_CLK_DELAY_MASK(0x0070)
+#define RGMII_TX_CLK_DELAY_POS (0)
+#define RGMII_TX_CLK_DELAY_WIDTH   (3)
+#define RGMII_TX_CLK_DELAY_MASK(0x0007)
+
+/* Extended Page 2 Register 27E2 */
+#define MSCC_PHY_WOL_MAC_CONTROL   27
+#define EDGE_RATE_CNTL_POS (5)
+#define EDGE_RATE_CNTL_WIDTH   (3)
+#define EDGE_RATE_CNTL_MASK(0x00E0)
+#define RMII_CLK_OUT_ENABLE_POS(4)
+#define RMII_CLK_OUT_ENABLE_WIDTH  (1)
+#define RMII_CLK_OUT_ENABLE_MASK   (0x10)
+
+/* Token Ring Page 0x52B5 Registers */
+#define MSCC_PHY_REG_TR_ADDR_1616
+#define MSCC_PHY_REG_TR_DATA_1717
+#define MSCC_PHY_REG_TR_DATA_1818
+
+/* Token Ring - Read Value in */
+#define MSCC_PHY_TR_16_READ(0xA000)
+/* Token Ring - Write Value out */
+#define MSCC_PHY_TR_16_WRITE   (0x8000)
+
+/* Token Ring Registers */
+#define MSCC_PHY_TR_LINKDETCTRL_POS(3)
+#define MSCC_PHY_TR_LINKDETCTRL_WIDTH  (2)
+#define MSCC_PHY_TR_LINKDETCTRL_VAL(3)
+#define MSCC_PHY_TR_LINKDETCTRL_MASK   (0x0018)
+#define MSCC_PHY_TR_LINKDETCTRL_ADDR   (0x07F8)
+
+#define MSCC_PHY_TR_VGATHRESH100_POS   (0)
+#define MSCC_PHY_TR_VGATHRESH100_WIDTH (7)
+#define MSCC_PHY_TR_VGATHRESH100_VAL   (0x0018)
+#define MSCC_PHY_TR_VGATHRESH100_MASK  (0x007f)
+#define MSCC_PHY_TR_VGATHRESH100_ADDR  (0x0FA4)
+
+#define MSCC_PHY_TR_VGAGAIN10_U_POS(0)
+#define MSCC_PHY_TR_VGAGAIN10_U_WIDTH