Re: [U-Boot] [PATCH v2 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[Dinh Nguyen]

On Thu, Oct 5, 2017 at 8:07 AM,   wrote:
> From: Chin Liang See 
>
> Add the base address map for Statix10 SoC
>
> Signed-off-by: Chin Liang See 
> ---
>  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 56 
> ++
>  1 file changed, 56 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
> b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> new file mode 100644
> index 000..2fdc917
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2016-2017 Intel Corporation 
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> +
> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xf8000400
> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS   0xf801
> +#define SOCFPGA_SDR_ADDRESS0xf8011000
> +#define SOCFPGA_SMMU_ADDRESS   0xfa00
> +#define SOCFPGA_MAILBOX_ADDRESS0xffA3
> +#define SOCFPGA_USB0_ADDRESS   0xffb0
> +#define SOCFPGA_USB1_ADDRESS   0xffb4

USB address is obtainable from DT.

> +#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
> +#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
> +#define SOCFPGA_UART0_ADDRESS  0xffc02000
> +#define SOCFPGA_UART1_ADDRESS  0xffc02100
> +#define SOCFPGA_I2C0_ADDRESS   0xffc02800
> +#define SOCFPGA_I2C1_ADDRESS   0xffc02900
> +#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
> +#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
> +#define SOCFPGA_I2C4_ADDRESS   0xffc02c00

I2C is also obtainabled

Please check the other peripherals.

Dinh
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[U-Boot] [PATCH v2 01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC

[chin . liang . see]

From: Chin Liang See 

Add the base address map for Statix10 SoC

Signed-off-by: Chin Liang See 
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 56 ++
 1 file changed, 56 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h 
b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100644
index 000..2fdc917
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation 
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS  0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS   0xf801
+#define SOCFPGA_SDR_ADDRESS0xf8011000
+#define SOCFPGA_SMMU_ADDRESS   0xfa00
+#define SOCFPGA_MAILBOX_ADDRESS0xffA3
+#define SOCFPGA_USB0_ADDRESS   0xffb0
+#define SOCFPGA_USB1_ADDRESS   0xffb4
+#define SOCFPGA_NANDREGS_ADDRESS   0xffb8
+#define SOCFPGA_NANDDATA_ADDRESS   0xffb9
+#define SOCFPGA_UART0_ADDRESS  0xffc02000
+#define SOCFPGA_UART1_ADDRESS  0xffc02100
+#define SOCFPGA_I2C0_ADDRESS   0xffc02800
+#define SOCFPGA_I2C1_ADDRESS   0xffc02900
+#define SOCFPGA_I2C2_ADDRESS   0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS   0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS   0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS   0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS   0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS  0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS  0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS  0xffd0
+#define SOCFPGA_SYSTIMER1_ADDRESS  0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS  0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS  0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS  0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS  0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd1
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA  0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA0xffd21300
+#define SOCFPGA_DMANONSECURE_ADDRESS   0xffda
+#define SOCFPGA_DMASECURE_ADDRESS  0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS  0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS  0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS  0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS  0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS  0xffe0
+#define GICD_BASE  0xfffc1000
+#define GICC_BASE  0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
-- 
2.2.2

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