Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Move setup_pch_gpios() to board support codes instead of
making it a weak function
arch/x86/include/asm/arch-coreboot/gpio.h | 3 ++
arch/x86/include/asm/arch-ivybridge/gpio.h | 3 ++
arch/x86/include/asm/gpio.h| 1 +
board/coreboot/coreboot/coreboot.c | 6
board/google/chromebook_link/link.c| 40 ++
drivers/gpio/intel_ich6_gpio.c | 53 ++
6 files changed, 55 insertions(+), 51 deletions(-)
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h
b/arch/x86/include/asm/arch-coreboot/gpio.h
index 4951a8c..31edef9 100644
--- a/arch/x86/include/asm/arch-coreboot/gpio.h
+++ b/arch/x86/include/asm/arch-coreboot/gpio.h
@@ -7,4 +7,7 @@
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h
b/arch/x86/include/asm/arch-ivybridge/gpio.h
index 4951a8c..31edef9 100644
--- a/arch/x86/include/asm/arch-ivybridge/gpio.h
+++ b/arch/x86/include/asm/arch-ivybridge/gpio.h
@@ -7,4 +7,7 @@
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
+/* Where in config space is the register that points to the GPIO registers? */
+#define PCI_CFG_GPIOBASE 0x48
+
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 5540d42..1787e52 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
#endif /* _X86_GPIO_H_ */
diff --git a/board/coreboot/coreboot/coreboot.c
b/board/coreboot/coreboot/coreboot.c
index 0240c34..b260f9a 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -6,6 +6,7 @@
#include common.h
#include cros_ec.h
+#include asm/gpio.h
int arch_early_init_r(void)
{
@@ -14,3 +15,8 @@ int arch_early_init_r(void)
return 0;
}
+
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
diff --git a/board/google/chromebook_link/link.c
b/board/google/chromebook_link/link.c
index 1822237..4d95c1c 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -7,6 +7,9 @@
#include common.h
#include cros_ec.h
#include asm/gpio.h
+#include asm/io.h
+#include asm/pci.h
+#include asm/arch/pch.h
int arch_early_init_r(void)
{
@@ -121,3 +124,40 @@ int board_early_init_f(void)
return 0;
}
+
+void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio)
+{
+ /* GPIO Set 1 */
+ if (gpio-set1.level)
+ outl(*((u32 *)gpio-set1.level), gpiobase + GP_LVL);
+ if (gpio-set1.mode)
+ outl(*((u32 *)gpio-set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio-set1.direction)
+ outl(*((u32 *)gpio-set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio-set1.reset)
+ outl(*((u32 *)gpio-set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio-set1.invert)
+ outl(*((u32 *)gpio-set1.invert), gpiobase + GPI_INV);
+ if (gpio-set1.blink)
+ outl(*((u32 *)gpio-set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio-set2.level)
+ outl(*((u32 *)gpio-set2.level), gpiobase + GP_LVL2);
+ if (gpio-set2.mode)
+ outl(*((u32 *)gpio-set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio-set2.direction)
+ outl(*((u32 *)gpio-set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio-set2.reset)
+ outl(*((u32 *)gpio-set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio-set3.level)
+ outl(*((u32 *)gpio-set3.level), gpiobase + GP_LVL3);
+ if (gpio-set3.mode)
+ outl(*((u32 *)gpio-set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio-set3.direction)
+ outl(*((u32 *)gpio-set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio-set3.reset)
+ outl(*((u32 *)gpio-set3.reset), gpiobase + GP_RST_SEL3);
+}
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b095d17..1f0d9df 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -34,16 +34,9 @@
#include asm/gpio.h
#include asm/io.h
#include asm/pci.h
-#ifdef CONFIG_X86_RESET_VECTOR
-#include asm/arch/pch.h
-#define SUPPORT_GPIO_SETUP
-#endif
#define GPIO_PER_BANK 32
-/* Where in config space is the register that points to
