Re: [U-Boot] [PATCH v2 1/2] arm: dts: Add devicetree support for iMXQXP AI_ML board
> Subject: [PATCH v2 1/2] arm: dts: Add devicetree support for iMXQXP AI_ML
> board
>
> Add devicetree support for iMXQXP AI_ML board from Einfochips.
>
> Signed-off-by: Manivannan Sadhasivam
>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi | 117 +
> arch/arm/dts/fsl-imx8qxp-ai_ml.dts | 181
> +
> 3 files changed, 299 insertions(+)
> create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
> create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> e6680e5e98..7834a158da 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -614,6 +614,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
> dtb-$(CONFIG_ARCH_IMX8) += \
> fsl-imx8qm-apalis.dtb \
> fsl-imx8qm-mek.dtb \
> + fsl-imx8qxp-ai_ml.dtb \
> fsl-imx8qxp-colibri.dtb \
> fsl-imx8qxp-mek.dtb
>
> diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
> b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
> new file mode 100644
> index 00..3ca53bb945
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Linaro Ltd.
> + */
> +
> +&{/imx8qx-pm} {
> +
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> +_lsio {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio0 {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio1 {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio2 {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio3 {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio4 {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio5 {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio6 {
> + u-boot,dm-spl;
> +};
> +
> +_lsio_gpio7 {
> + u-boot,dm-spl;
> +};
> +
> +_conn {
> + u-boot,dm-spl;
> +};
> +
> +_conn_sdch0 {
> + u-boot,dm-spl;
> +};
> +
> +_conn_sdch1 {
> + u-boot,dm-spl;
> +};
> +
> +_conn_sdch2 {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> +
> + {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
> b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
> new file mode 100644
> index 00..aa85caaff5
> --- /dev/null
> +++ b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
> @@ -0,0 +1,181 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 Einfochips
> + * Copyright 2019 Linaro Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-imx8qxp.dtsi"
> +#include "fsl-imx8qxp-ai_ml-u-boot.dtsi"
> +
> +/ {
> + model = "Einfochips i.MX8QXP AI_ML";
> + compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
> +
> + chosen {
> + bootargs = "console=ttyLP2,115200
> earlycon=lpuart32,0x5a08,115200";
> + stdout-path =
> + };
> +
> + memory@8000 {
> + device_type = "memory";
> + reg = <0x 0x8000 0 0x8000>;
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_lpuart0>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_lpuart1>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_lpuart2>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_lpuart3>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_fec1>;
> + phy-mode = "rgmii";
> + phy-handle = <>;
> + fsl,ar8031-phy-fixup;
> + fsl,magic-packet;
> + phy-reset-gpios = < 14 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <10>;
> + phy-reset-post-delay = <150>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> + };
> +};
> +
> +/* LS-I2C1 */
> + {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <10>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_lpi2c1>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_usdhc1>;
> + bus-width = <4>;
> + no-sd;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_usdhc2>;
> + bus-width = <4>;
> + cd-gpios = < 22
[U-Boot] [PATCH v2 1/2] arm: dts: Add devicetree support for iMXQXP AI_ML board
Add devicetree support for iMXQXP AI_ML board from Einfochips.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi | 117 +
arch/arm/dts/fsl-imx8qxp-ai_ml.dts | 181 +
3 files changed, 299 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
create mode 100644 arch/arm/dts/fsl-imx8qxp-ai_ml.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e6680e5e98..7834a158da 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -614,6 +614,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
+ fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
fsl-imx8qxp-mek.dtb
diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
new file mode 100644
index 00..3ca53bb945
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-ai_ml-u-boot.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Linaro Ltd.
+ */
+
+&{/imx8qx-pm} {
+
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_lsio {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+_conn {
+ u-boot,dm-spl;
+};
+
+_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
new file mode 100644
index 00..aa85caaff5
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-ai_ml.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Einfochips
+ * Copyright 2019 Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-ai_ml-u-boot.dtsi"
+
+/ {
+ model = "Einfochips i.MX8QXP AI_ML";
+ compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP2,115200
earlycon=lpuart32,0x5a08,115200";
+ stdout-path =
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x 0x8000 0 0x8000>;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart0>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart1>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart2>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpuart3>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fec1>;
+ phy-mode = "rgmii";
+ phy-handle = <>;
+ fsl,ar8031-phy-fixup;
+ fsl,magic-packet;
+ phy-reset-gpios = < 14 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ phy-reset-post-delay = <150>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
+/* LS-I2C1 */
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_lpi2c1>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc1>;
+ bus-width = <4>;
+ no-sd;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_usdhc2>;
+ bus-width = <4>;
+ cd-gpios = < 22 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+ {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD
0x14a0
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD
0x14a0
+ SC_P_ENET0_MDC_CONN_ENET0_MDC
0x0620
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO
