Re: [U-Boot] [PATCH v2 1/2] spi: sunxi_spi: Add DM SPI driver for A31/A80/A64
On Thu, Mar 2, 2017 at 2:59 AM, Philipp Tomsich
wrote:
> This adds a rewrite of the SPI driver we had in use for the A31-uQ7
> (sun6i), A80-Q7 (sun9i) and A64-uQ7 (sun50i) boards, which includes
> support for:
> * cs-gpios (i.e. GPIOs as additional chip-selects)
> * clocking, reset and pinctrl based on the device-model
> * dual-IO data receive for controllers that support it (sun50i)
>
> The key difference to the earlier incarnation that we provided as part
> of our BSP is the removal of the legacy reset and clocking code and
> added resilience to configuration errors (i.e. timeouts for the inner
> loops) and converstion to the device-model. This was possible due to a
> non-device-model driver now being present for use with in the SPL.
>
> This has been verified against the A64-uQ7 with data rates up to
> 100MHz and dual-IO ("Fast Read Dual Output" opcode) from the on-board
> SPI-NOR flash.
>
> Signed-off-by: Philipp Tomsich
> ---
> drivers/spi/Kconfig | 14 ++
> drivers/spi/Makefile| 1 +
> drivers/spi/sunxi_spi.c | 516
>
> 3 files changed, 531 insertions(+)
> create mode 100644 drivers/spi/sunxi_spi.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index f3f7dbe..64b6430 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -132,6 +132,20 @@ config STM32_QSPI
> used to access the SPI NOR flash chips on platforms embedding
> this ST IP core.
>
> +config SUNXI_SPI
> + bool "Allwinner (sunxi) SPI driver"
> + help
> + Enable the SPI driver for Allwinner SoCs.
> +
> + This driver can be used to access the SPI NOR flash on for
> + communciation with SPI peripherals platforms embedding the
> + Allwinner SoC. This driver supports the device-model (only)
> + and has support for GPIOs as additional chip-selects.
> +
> + For recent platforms (e.g. sun50i), dual-IO receive mode is
> + also supported, when configured for a SPI-NOR flash in the
> + device tree.
> +
> config TEGRA114_SPI
> bool "nVidia Tegra114 SPI driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index fa9a1d2..aab31b4 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -40,6 +40,7 @@ obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
> obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
> obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
> obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
> +obj-$(CONFIG_SUNXI_SPI) += sunxi_spi.o
Is this the common spi driver for sunxi, I'm sure it's specific to 6i,
better name the same. If all yes, try to use the macro names in Linux
spi driver.
> obj-$(CONFIG_SH_SPI) += sh_spi.o
> obj-$(CONFIG_SH_QSPI) += sh_qspi.o
> obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
> diff --git a/drivers/spi/sunxi_spi.c b/drivers/spi/sunxi_spi.c
> new file mode 100644
> index 000..f26becf
> --- /dev/null
> +++ b/drivers/spi/sunxi_spi.c
> @@ -0,0 +1,516 @@
> +/*
> + * SPI driver for Allwinner sunxi SoCs
> + *
> + * Copyright (C) 2015-2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include
> +#ifdef CONFIG_DM_GPIO
> +#include
> +#endif
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct sunxi_spi_platdata {
> + void *base;
> + unsigned int max_hz;
> +
> + struct reset_ctl reset_ctl;
> + struct clk ahb_clk_gate;
> + struct clk spi_clk;
> +
> + /* We could do with a single delay counter, but it won't do harm
> + to have two, as the same is the case for most other driver. */
> + uint deactivate_delay_us; /* Delay to wait after deactivate */
> + uint activate_delay_us; /* Delay to wait after activate */
> +
> +#if defined(CONFIG_DM_GPIO)
> + int cs_gpios_num;
> + struct gpio_desc *cs_gpios;
> +#endif
> +};
> +
> +struct sunxi_spi_driverdata {
> + unsigned int fifo_depth;
> +};
> +
> +struct sunxi_spi_privdata {
> + ulong last_transaction_us; /* Time of last transaction end */
> + unsigned int hz_requested; /* last requested bitrate */
> + unsigned int hz_actual; /* currently set bitrate */
> +};
> +
> +struct sunxi_spi_reg {
> + u8 _rsvd[0x4];
> + u32 GCR; /* SPI Global Control register */
> + u32 TCR; /* SPI Transfer Control register */
> + u8 _rsvd1[0x4];
> + u32 IER; /* SPI Interrupt Control register */
> + u32 ISR; /* SPI Interrupt Status register */
> + u32 FCR; /* SPI FIFO Control register */
> + u32 FSR; /* SPI FIFO Status r
[U-Boot] [PATCH v2 1/2] spi: sunxi_spi: Add DM SPI driver for A31/A80/A64
This adds a rewrite of the SPI driver we had in use for the A31-uQ7
(sun6i), A80-Q7 (sun9i) and A64-uQ7 (sun50i) boards, which includes
support for:
* cs-gpios (i.e. GPIOs as additional chip-selects)
* clocking, reset and pinctrl based on the device-model
* dual-IO data receive for controllers that support it (sun50i)
The key difference to the earlier incarnation that we provided as part
of our BSP is the removal of the legacy reset and clocking code and
added resilience to configuration errors (i.e. timeouts for the inner
loops) and converstion to the device-model. This was possible due to a
non-device-model driver now being present for use with in the SPL.
This has been verified against the A64-uQ7 with data rates up to
100MHz and dual-IO ("Fast Read Dual Output" opcode) from the on-board
SPI-NOR flash.
Signed-off-by: Philipp Tomsich
---
drivers/spi/Kconfig | 14 ++
drivers/spi/Makefile| 1 +
drivers/spi/sunxi_spi.c | 516
3 files changed, 531 insertions(+)
create mode 100644 drivers/spi/sunxi_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f3f7dbe..64b6430 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -132,6 +132,20 @@ config STM32_QSPI
used to access the SPI NOR flash chips on platforms embedding
this ST IP core.
+config SUNXI_SPI
+ bool "Allwinner (sunxi) SPI driver"
+ help
+ Enable the SPI driver for Allwinner SoCs.
+
+ This driver can be used to access the SPI NOR flash on for
+ communciation with SPI peripherals platforms embedding the
+ Allwinner SoC. This driver supports the device-model (only)
+ and has support for GPIOs as additional chip-selects.
+
+ For recent platforms (e.g. sun50i), dual-IO receive mode is
+ also supported, when configured for a SPI-NOR flash in the
+ device tree.
+
config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fa9a1d2..aab31b4 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
+obj-$(CONFIG_SUNXI_SPI) += sunxi_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
diff --git a/drivers/spi/sunxi_spi.c b/drivers/spi/sunxi_spi.c
new file mode 100644
index 000..f26becf
--- /dev/null
+++ b/drivers/spi/sunxi_spi.c
@@ -0,0 +1,516 @@
+/*
+ * SPI driver for Allwinner sunxi SoCs
+ *
+ * Copyright (C) 2015-2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include
+#ifdef CONFIG_DM_GPIO
+#include
+#endif
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sunxi_spi_platdata {
+ void *base;
+ unsigned int max_hz;
+
+ struct reset_ctl reset_ctl;
+ struct clk ahb_clk_gate;
+ struct clk spi_clk;
+
+ /* We could do with a single delay counter, but it won't do harm
+ to have two, as the same is the case for most other driver. */
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
+ uint activate_delay_us; /* Delay to wait after activate */
+
+#if defined(CONFIG_DM_GPIO)
+ int cs_gpios_num;
+ struct gpio_desc *cs_gpios;
+#endif
+};
+
+struct sunxi_spi_driverdata {
+ unsigned int fifo_depth;
+};
+
+struct sunxi_spi_privdata {
+ ulong last_transaction_us; /* Time of last transaction end */
+ unsigned int hz_requested; /* last requested bitrate */
+ unsigned int hz_actual; /* currently set bitrate */
+};
+
+struct sunxi_spi_reg {
+ u8 _rsvd[0x4];
+ u32 GCR; /* SPI Global Control register */
+ u32 TCR; /* SPI Transfer Control register */
+ u8 _rsvd1[0x4];
+ u32 IER; /* SPI Interrupt Control register */
+ u32 ISR; /* SPI Interrupt Status register */
+ u32 FCR; /* SPI FIFO Control register */
+ u32 FSR; /* SPI FIFO Status register */
+ u32 WCR; /* SPI Wait Clock Counter register */
+ u32 CCR; /* SPI Clock Rate Control register */
+ u8 _rsvd2[0x8];
+ u32 MBC; /* SPI Burst Counter register */
+ u32 MTC; /* SPI Transmit Counter register */
+ u32 BCC; /* SPI Burst Control register */
+ u8 _rsvd3[0x4c];
+ u32 NDMA_MODE_CTL;
+ u8 _rsvd4[0x174];
+ u32 TXD; /* SPI TX Data register
