Re: [U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

2009-09-11 Thread Wolfgang Denk 
Dear Mingkai Hu,

In message 1252639077-29277-1-git-send-email-mingkai...@freescale.com you 
wrote:
 The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
 implements these three bootup methods in a unified way - all of these
 use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
 which lets us use the SPD to initialize the SDRAM.

...

I'm confused.

Is this v2 reposted? Or an updated version?

Could you please be so kind and always note (below the --- line)
what has changed against the previous version of the patch?

Thanks.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

2009-09-11 Thread Scott Wood 
Mingkai Hu wrote:
 The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
 implements these three bootup methods in a unified way - all of these
 use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
 which lets us use the SPD to initialize the SDRAM.
 
 For all three bootup methods, the bootup process can be divided into two
 stages: the first stage will initialize the corresponding controller,
 configure the L2SRAM, then copy the second stage image to L2SRAM and
 jump to it. The second stage image is just like the general U-Boot image
 to configure all the hardware and boot up to U-Boot command line.
 
 When boot from NAND, the eLBC controller will first load the first stage
 image to internal 4K RAM buffer because it's also stored on the NAND
 flash. The first stage image, also call 4K NADN loader, will initialize

s/NADN/NAND/ here...

 +#ifdef CONFIG_NADN_SPL
  static void tlbsx (const volatile unsigned *addr)

And more importantly, here.

-Scott
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Re: [U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

2009-09-11 Thread Kumar Gala 

On Sep 11, 2009, at 1:06 PM, Scott Wood wrote:

 Mingkai Hu wrote:
 The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
 implements these three bootup methods in a unified way - all of these
 use the general cpu/mpc85xx/start.S, and load the main image to  
 L2SRAM
 which lets us use the SPD to initialize the SDRAM.

 For all three bootup methods, the bootup process can be divided  
 into two
 stages: the first stage will initialize the corresponding controller,
 configure the L2SRAM, then copy the second stage image to L2SRAM and
 jump to it. The second stage image is just like the general U-Boot  
 image
 to configure all the hardware and boot up to U-Boot command line.

 When boot from NAND, the eLBC controller will first load the first  
 stage
 image to internal 4K RAM buffer because it's also stored on the NAND
 flash. The first stage image, also call 4K NADN loader, will  
 initialize

 s/NADN/NAND/ here...

will fix this one.

 +#ifdef CONFIG_NADN_SPL
 static void tlbsx (const volatile unsigned *addr)

 And more importantly, here.

I've fixed that one.. see my latest v4 patch.

- k
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[U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

2009-09-10 Thread Mingkai Hu 
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NADN loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
 cpu/mpc85xx/cpu_init.c |   19 +++
 cpu/mpc85xx/start.S|   23 ++-
 cpu/mpc85xx/tlb.c  |6 ++
 drivers/misc/fsl_law.c |2 ++
 4 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a54cf5d..5f66511 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -291,6 +291,25 @@ int cpu_init_r(void)
 
asm(msync;isync);
cache_ctl = l2cache-l2ctl;
+
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L2_ADDR)
+   if (cache_ctl  MPC85xx_L2CTL_L2E) {
+   /* Clear L2 SRAM memory-mapped base address */
+   out_be32(l2cache-l2srbar0, 0x0);
+   out_be32(l2cache-l2srbar1, 0x0);
+
+   /* set MBECCDIS=0, SBECCDIS=0 */
+   clrbits_be32(l2cache-l2errdis,
+   (MPC85xx_L2ERRDIS_MBECC |
+MPC85xx_L2ERRDIS_SBECC));
+
+   /* set L2E=0, L2SRAM=0 */
+   clrbits_be32(l2cache-l2ctl,
+   (MPC85xx_L2CTL_L2E |
+MPC85xx_L2CTL_L2SRAM_ENTIRE));
+   }
+#endif
+
l2siz_field = (cache_ctl  28)  0x3;
 
switch (l2siz_field) {
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e21a4eb..c5b6bd9 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -57,10 +57,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
 
+#ifndef CONFIG_NAND_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
+#endif
 
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -235,10 +237,11 @@ _start_e500:
 
 #endif /* CONFIG_MPC8569 */
 
-   /* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
+#ifndef CONFIG_SYS_RAMBOOT
+   /* create a temp mapping in AS=1 to the 4M boot window */
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
 
@@ -248,6 +251,20 @@ _start_e500:
/* The 85xx has the default boot window 0xff80 - 0x */
lis r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+   /*
+* create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
+* image has been relocated to TEXT_BASE on the second stage.
+*/
+   lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+   ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+   lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+   ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+   lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+   ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
 
mtspr   MAS0,r6
mtspr   MAS1,r7
@@ -359,6 +376,7 @@ _start_cont:
bl  board_init_f
isync
 
+#ifndef CONFIG_NAND_SPL
. = EXC_OFF_SYS_RESET
.globl  _start_of_vectors
 _start_of_vectors:
@@ -813,6 +831,7 @@ in32:
 in32r:
lwbrx   r3,r0,r3
blr
+#endif  /* !CONFIG_NAND_SPL */

Re: [U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

2009-09-10 Thread Kumar Gala 

On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:

 diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
 index 0497a29..9c7c928 100644
 --- a/cpu/mpc85xx/tlb.c
 +++ b/cpu/mpc85xx/tlb.c
 @@ -59,6 +59,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 #endif
 }

 +#ifndef CONFIG_NAND_SPL
 void disable_tlb(u8 esel)
 {
   u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 @@ -83,6 +84,7 @@ void disable_tlb(u8 esel)
   addrmap_set_entry(0, 0, 0, esel);
 #endif
 }
 +#endif

 void invalidate_tlb(u8 tlb)
 {
 @@ -106,6 +108,7 @@ void init_tlbs(void)
   return ;
 }

 +#ifdef CONFIG_ADDR_MAP

why ADDR_MAP?

- k

 static void tlbsx (const volatile unsigned *addr)
 {
   __asm__ __volatile__ (tlbsx 0,%0 : : r (addr), m (*addr));
 @@ -132,6 +135,7 @@ int find_tlb_idx(void *addr, u8 tlbsel)

   return -1;
 }
 +#endif

 #ifdef CONFIG_ADDR_MAP
 void init_addr_map(void)
 @@ -168,6 +172,7 @@ void init_addr_map(void)
 }
 #endif

 +#ifndef CONFIG_NAND_SPL
 #ifndef CONFIG_SYS_DDR_TLB_START
 #define CONFIG_SYS_DDR_TLB_START 8
 #endif
 @@ -215,3 +220,4 @@ unsigned int setup_ddr_tlbs(unsigned int  
 memsize_in_meg)
*/
   return memsize_in_meg;
 }
 +#endif /* !CONFIG_NAND_SPL */

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Re: [U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

2009-09-10 Thread Hu Mingkai-B21284 
 

 -Original Message-
 From: Gala Kumar-B11780 
 Sent: Friday, September 11, 2009 11:13 AM
 To: Hu Mingkai-B21284
 Cc: u-boot@lists.denx.de; Wood Scott-B07421
 Subject: Re: [PATCH v2 1/5] 85xx: add boot from 
 NAND/eSDHC/eSPI support
 
 
 On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:
 
  diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 
  0497a29..9c7c928 100644
  --- a/cpu/mpc85xx/tlb.c
  +++ b/cpu/mpc85xx/tlb.c
  @@ -59,6 +59,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, #endif }
 
  +#ifndef CONFIG_NAND_SPL
  void disable_tlb(u8 esel)
  {
  u32 _mas0, _mas1, _mas2, _mas3, _mas7; @@ -83,6 +84,7 @@ void 
  disable_tlb(u8 esel)
  addrmap_set_entry(0, 0, 0, esel);
  #endif
  }
  +#endif
 
  void invalidate_tlb(u8 tlb)
  {
  @@ -106,6 +108,7 @@ void init_tlbs(void)
  return ;
  }
 
  +#ifdef CONFIG_ADDR_MAP
 
 why ADDR_MAP?
 

Oh..., sorry, copy error, it should be NAND_SPL. I'll send it again.

Without this, the 4K NAND loader size will over 4K.

Thanks,
Mingkai
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[U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

2009-09-10 Thread Mingkai Hu 
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NADN loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
 cpu/mpc85xx/cpu_init.c |   19 +++
 cpu/mpc85xx/start.S|   23 ++-
 cpu/mpc85xx/tlb.c  |6 ++
 drivers/misc/fsl_law.c |2 ++
 4 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a54cf5d..5f66511 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -291,6 +291,25 @@ int cpu_init_r(void)
 
asm(msync;isync);
cache_ctl = l2cache-l2ctl;
+
+#if defined(CONFIG_SYS_RAMBOOT)  defined(CONFIG_SYS_INIT_L2_ADDR)
+   if (cache_ctl  MPC85xx_L2CTL_L2E) {
+   /* Clear L2 SRAM memory-mapped base address */
+   out_be32(l2cache-l2srbar0, 0x0);
+   out_be32(l2cache-l2srbar1, 0x0);
+
+   /* set MBECCDIS=0, SBECCDIS=0 */
+   clrbits_be32(l2cache-l2errdis,
+   (MPC85xx_L2ERRDIS_MBECC |
+MPC85xx_L2ERRDIS_SBECC));
+
+   /* set L2E=0, L2SRAM=0 */
+   clrbits_be32(l2cache-l2ctl,
+   (MPC85xx_L2CTL_L2E |
+MPC85xx_L2CTL_L2SRAM_ENTIRE));
+   }
+#endif
+
l2siz_field = (cache_ctl  28)  0x3;
 
switch (l2siz_field) {
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e21a4eb..c5b6bd9 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -57,10 +57,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
 
+#ifndef CONFIG_NAND_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
+#endif
 
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -235,10 +237,11 @@ _start_e500:
 
 #endif /* CONFIG_MPC8569 */
 
-   /* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
+#ifndef CONFIG_SYS_RAMBOOT
+   /* create a temp mapping in AS=1 to the 4M boot window */
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
 
@@ -248,6 +251,20 @@ _start_e500:
/* The 85xx has the default boot window 0xff80 - 0x */
lis r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+   /*
+* create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
+* image has been relocated to TEXT_BASE on the second stage.
+*/
+   lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+   ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+   lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+   ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+   lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+   ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
 
mtspr   MAS0,r6
mtspr   MAS1,r7
@@ -359,6 +376,7 @@ _start_cont:
bl  board_init_f
isync
 
+#ifndef CONFIG_NAND_SPL
. = EXC_OFF_SYS_RESET
.globl  _start_of_vectors
 _start_of_vectors:
@@ -813,6 +831,7 @@ in32:
 in32r:
lwbrx   r3,r0,r3
blr
+#endif  /* !CONFIG_NAND_SPL */