Re: [U-Boot] [PATCH v2 2/4] gw_ventana: Move the DCD settings to spl code

2014-12-04 Thread Stefan Roese 

Hi Fabio, Hi Tim,

On 14.11.2014 12:37, Fabio Estevam wrote:

From: Fabio Estevam 

mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.


While reworking another mx6 based board (patches will follow soon), I 
noticed a problem with this patch. Please see below.



Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Newly introduced on this series

  board/gateworks/gw_ventana/clocks.cfg   | 42 -
  board/gateworks/gw_ventana/gw_ventana.cfg   |  6 -
  board/gateworks/gw_ventana/gw_ventana_spl.c | 28 +++
  3 files changed, 28 insertions(+), 48 deletions(-)
  delete mode 100644 board/gateworks/gw_ventana/clocks.cfg

diff --git a/board/gateworks/gw_ventana/clocks.cfg 
b/board/gateworks/gw_ventana/clocks.cfg
deleted file mode 100644
index a8118a2..000
--- a/board/gateworks/gw_ventana/clocks.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 Gateworks Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type   AddressValue
- *
- * where:
- *  Addr-type register length (1,2 or 4 bytes)
- *  Address   absolute address of the register
- *  value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF0
-DATA 4, CCM_CCGR4, 0xF300 /* enable NAND/GPMI/BCH clocks */


Notice here the 0xF300...


-DATA 4, CCM_CCGR5, 0x0FC3
-DATA 4, CCM_CCGR6, 0x03FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF0CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1--> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x00fb
diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg 
b/board/gateworks/gw_ventana/gw_ventana.cfg
index 9ab95f5..dd8aa61 100644
--- a/board/gateworks/gw_ventana/gw_ventana.cfg
+++ b/board/gateworks/gw_ventana/gw_ventana.cfg
@@ -21,9 +21,3 @@ BOOT_FROM  spi
  #else
  BOOT_FROM  nand
  #endif
-
-#define __ASSEMBLY__
-#include 
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-#include "clocks.cfg"
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c 
b/board/gateworks/gw_ventana/gw_ventana_spl.c
index ca35b3c..d6a5847 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -8,6 +8,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int 
board_model)
mx6_dram_cfg(&sysinfo, calib, mem);
  }

+static void ccgr_init(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   writel(0x00C03F3F, &ccm->CCGR0);
+   writel(0x0030FC03, &ccm->CCGR1);
+   writel(0x0FFFC000, &ccm->CCGR2);
+   writel(0x3FF0, &ccm->CCGR3);
+   writel(0x00FFF300, &ccm->CCGR4);


... and now here the 0x00FFF300! I'm pretty sure that it should be the 
same value as above. Otherwise NAND booting will not work correctly. At 
least from my experience.


I'll send a patch to fix this shortly...

Thanks,
Stefan

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Re: [U-Boot] [PATCH v2 2/4] gw_ventana: Move the DCD settings to spl code

2014-11-20 Thread Stefano Babic 
On 14/11/2014 12:37, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
> 
> Move the configuration to the spl code.
> 
> CCM_CCOSR setting is no longer required to get audio functionality in the
> kernel, so remove such setting.
> 
> Signed-off-by: Fabio Estevam 
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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[U-Boot] [PATCH v2 2/4] gw_ventana: Move the DCD settings to spl code

2014-11-14 Thread Fabio Estevam 
From: Fabio Estevam 

mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.

Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Newly introduced on this series

 board/gateworks/gw_ventana/clocks.cfg   | 42 -
 board/gateworks/gw_ventana/gw_ventana.cfg   |  6 -
 board/gateworks/gw_ventana/gw_ventana_spl.c | 28 +++
 3 files changed, 28 insertions(+), 48 deletions(-)
 delete mode 100644 board/gateworks/gw_ventana/clocks.cfg

diff --git a/board/gateworks/gw_ventana/clocks.cfg 
b/board/gateworks/gw_ventana/clocks.cfg
deleted file mode 100644
index a8118a2..000
--- a/board/gateworks/gw_ventana/clocks.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 Gateworks Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type   AddressValue
- *
- * where:
- *  Addr-type register length (1,2 or 4 bytes)
- *  Address   absolute address of the register
- *  value value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF0
-DATA 4, CCM_CCGR4, 0xF300 /* enable NAND/GPMI/BCH clocks */
-DATA 4, CCM_CCGR5, 0x0FC3
-DATA 4, CCM_CCGR6, 0x03FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF0CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1--> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x00fb
diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg 
b/board/gateworks/gw_ventana/gw_ventana.cfg
index 9ab95f5..dd8aa61 100644
--- a/board/gateworks/gw_ventana/gw_ventana.cfg
+++ b/board/gateworks/gw_ventana/gw_ventana.cfg
@@ -21,9 +21,3 @@ BOOT_FROM  spi
 #else
 BOOT_FROM  nand
 #endif
-
-#define __ASSEMBLY__
-#include 
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-#include "clocks.cfg"
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c 
b/board/gateworks/gw_ventana/gw_ventana_spl.c
index ca35b3c..d6a5847 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int 
board_model)
mx6_dram_cfg(&sysinfo, calib, mem);
 }
 
+static void ccgr_init(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   writel(0x00C03F3F, &ccm->CCGR0);
+   writel(0x0030FC03, &ccm->CCGR1);
+   writel(0x0FFFC000, &ccm->CCGR2);
+   writel(0x3FF0, &ccm->CCGR3);
+   writel(0x00FFF300, &ccm->CCGR4);
+   writel(0x0FC3, &ccm->CCGR5);
+   writel(0x03FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+   struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+   /* enable AXI cache for VDOA/VPU/IPU */
+   writel(0xF0CF, &iomux->gpr[4]);
+   /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+   writel(0x007F007F, &iomux->gpr[6]);
+   writel(0x007F007F, &iomux->gpr[7]);
+}
+
 /*
  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  * - we have a stack and a place to store GD, both in SRAM
@@ -405,6 +430,9 @@ void board_init_f(ulong dummy)
/* setup AIPS and disable watchdog */
arch_cpu_init();
 
+   ccgr_init();
+   gpr_init();
+
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
-- 
1.9.1

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