Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- New patch.
arch/arm/cpu/armv7/exynos/clock.c | 82 +++
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 519928c..6a1b05f 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -267,6 +267,46 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return fout;
}
+/* exynos5420: return pll clock frequency */
+static unsigned long exynos542x_get_pll_clk(int pllreg)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(clk-apll_con0);
+ break;
+ case MPLL:
+ r = readl(clk-mpll_con0);
+ break;
+ case EPLL:
+ r = readl(clk-epll_con0);
+ k = readl(clk-epll_con1);
+ break;
+ case VPLL:
+ r = readl(clk-vpll_con0);
+ k = readl(clk-vpll_con1);
+ break;
+ case BPLL:
+ r = readl(clk-bpll_con0);
+ break;
+ case RPLL:
+ r = readl(clk-rpll_con0);
+ k = readl(clk-rpll_con1);
+ break;
+ case SPLL:
+ r = readl(clk-spll_con0);
+ break;
+ default:
+ printf(Unsupported PLL (%d)\n, pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
static struct clk_bit_info *get_clk_bit_info(int peripheral)
{
int i;
@@ -383,46 +423,6 @@ unsigned long clock_get_periph_rate(int peripheral)
return 0;
}
-/* exynos5420: return pll clock frequency */
-static unsigned long exynos5420_get_pll_clk(int pllreg)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
-
- switch (pllreg) {
- case APLL:
- r = readl(clk-apll_con0);
- break;
- case MPLL:
- r = readl(clk-mpll_con0);
- break;
- case EPLL:
- r = readl(clk-epll_con0);
- k = readl(clk-epll_con1);
- break;
- case VPLL:
- r = readl(clk-vpll_con0);
- k = readl(clk-vpll_con1);
- break;
- case BPLL:
- r = readl(clk-bpll_con0);
- break;
- case RPLL:
- r = readl(clk-rpll_con0);
- k = readl(clk-rpll_con1);
- break;
- case SPLL:
- r = readl(clk-spll_con0);
- break;
- default:
- printf(Unsupported PLL (%d)\n, pllreg);
- return 0;
- }
-
- return exynos_get_pll_clk(pllreg, r, k);
-}
-
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@@ -1604,7 +1604,7 @@ unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pll_clk(pllreg);
+ return exynos542x_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
if (proid_is_exynos4412())
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
