This provides SPL support for T30 boards - AVP early init, plus
CPU (A9) init/jump to main U-Boot.
Some changes were made to Tegra20 cpu.c to move common routines
into tegra-common/cpu.c and reduce code duplication.
Signed-off-by: Tom Warren twar...@nvidia.com
---
V2: Move common CPU init code to tegra-common/cpu.c
arch/arm/cpu/arm720t/tegra-common/Makefile |1 +
arch/arm/cpu/arm720t/tegra-common/cpu.c| 342
arch/arm/cpu/arm720t/tegra-common/cpu.h| 64 ++
arch/arm/cpu/arm720t/tegra-common/spl.c|3 +-
arch/arm/cpu/arm720t/tegra20/cpu.c | 216 ++
arch/arm/cpu/arm720t/tegra30/Makefile | 41
arch/arm/cpu/arm720t/tegra30/config.mk | 19 ++
arch/arm/cpu/arm720t/tegra30/cpu.c | 176 ++
8 files changed, 615 insertions(+), 247 deletions(-)
create mode 100644 arch/arm/cpu/arm720t/tegra-common/cpu.c
create mode 100644 arch/arm/cpu/arm720t/tegra30/Makefile
create mode 100644 arch/arm/cpu/arm720t/tegra30/config.mk
create mode 100644 arch/arm/cpu/arm720t/tegra30/cpu.c
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile
b/arch/arm/cpu/arm720t/tegra-common/Makefile
index febd2e3..6cbc6ad 100644
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ b/arch/arm/cpu/arm720t/tegra-common/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)libtegra-common.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
+COBJS-y+= cpu.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c
b/arch/arm/cpu/arm720t/tegra-common/cpu.c
new file mode 100644
index 000..2fbe02b
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/gp_padctrl.h
+#include asm/arch/pinmux.h
+#include asm/arch/tegra.h
+#include asm/arch-tegra/clk_rst.h
+#include asm/arch-tegra/pmc.h
+#include asm/arch-tegra/scu.h
+#include cpu.h
+
+enum tegra_family_t {
+ TEGRA_FAMILY_T2x,
+ TEGRA_FAMILY_T3x,
+};
+
+
+enum tegra_family_t get_family(void)
+{
+ u32 reg, chip_id;
+
+ reg = readl(NV_PA_APB_MISC_BASE + GP_HIDREV);
+
+ chip_id = reg 8;
+ chip_id = 0xff;
+ debug( tegra_get_family: chip_id = %x\n, chip_id);
+ if (chip_id == 0x30)
+ return TEGRA_FAMILY_T3x;
+ else
+ return TEGRA_FAMILY_T2x;
+}
+
+int get_num_cpus(void)
+{
+ return get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
+}
+
+/*
+ * Timing tables for each SOC for all four oscillator options.
+ */
+struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
+ /* T20: 1 GHz */
+ {{ 1000, 13, 0, 12},/* OSC 13M */
+{ 625, 12, 0, 8}, /* OSC 19.2M */
+{ 1000, 12, 0, 12},/* OSC 12M */
+{ 1000, 26, 0, 12},/* OSC 26M */
+ },
+
+ /* T25: 1.2 GHz */
+ {{ 923, 10, 0, 12},
+{ 750, 12, 0, 8},
+{ 600, 6, 0, 12},
+{ 600, 13, 0, 12},
+ },
+
+ /* T30(slow): 1.0 GHz */
+ {{ 1000, 13, 0, 8},
+{ 625, 12, 0, 4},
+{ 1000, 12, 0, 8},
+{ 1000, 26, 0, 8},
+ },
+
+ /* T30(high): 1.4 GHz */
+ {{ 862, 8, 0, 8},
+{ 583, 8, 0, 4},
+{ 700, 6, 0, 8},
+{ 700, 13, 0, 8},
+ },
+
+ /* TEGRA_SOC2_SLOW: 312 MHz */
+ {{ 312, 13, 0, 12}, /* OSC 13M */
+{ 260, 16, 0, 8}, /* OSC 19.2M */
+{ 312, 12, 0, 12}, /* OSC 12M */
+{ 312, 26, 0, 12}, /* OSC 26M */
+ },
+};
+
+void adjust_pllp_out_freqs(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll *pll = clkrst-crc_pll[CLOCK_ID_PERIPH];
+ u32 reg;
+
+ /* Set T30 PLLP_OUT1, 2, 3 4 freqs to 9.6, 48, 102 204MHz */
+ reg = readl(pll-pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
+ reg |= (IN_408_OUT_48_DIVISOR PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
+ | (IN_408_OUT_9_6_DIVISOR PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
+ writel(reg, pll-pll_out[0]);
+
+ reg = readl(pll-pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
+ reg |= (IN_408_OUT_204_DIVISOR PLLP_OUT4_RATIO) |
