Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported).
It also adds a Kconfig skeleton to later add more SECO board (supporting
SoC and board variants).
Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com
---
arch/arm/cpu/armv7/mx6/Kconfig| 11 +++
board/seco/Kconfig| 63 ++
board/seco/common/Makefile| 2 +
board/seco/common/mx6.c | 138 ++
board/seco/common/mx6.h | 9 ++
board/seco/mx6quq7/MAINTAINERS| 6 ++
board/seco/mx6quq7/Makefile | 7 ++
board/seco/mx6quq7/mx6quq7-2g.cfg | 173 ++
board/seco/mx6quq7/mx6quq7.c | 162 +++
configs/secomx6quq7_defconfig | 7 ++
include/configs/secomx6quq7.h | 166
11 files changed, 744 insertions(+)
create mode 100644 board/seco/Kconfig
create mode 100644 board/seco/common/Makefile
create mode 100644 board/seco/common/mx6.c
create mode 100644 board/seco/common/mx6.h
create mode 100644 board/seco/mx6quq7/MAINTAINERS
create mode 100644 board/seco/mx6quq7/Makefile
create mode 100644 board/seco/mx6quq7/mx6quq7-2g.cfg
create mode 100644 board/seco/mx6quq7/mx6quq7.c
create mode 100644 configs/secomx6quq7_defconfig
create mode 100644 include/configs/secomx6quq7.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index a32fd87..076ba52 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -25,7 +25,18 @@ config MX6SL
config MX6SX
bool
+choice
+ prompt MX6 board select
+
+config TARGET_SECOMX6
+ bool Support secomx6 boards
+ select CPU_V7
+
+endchoice
+
config SYS_SOC
default mx6
+source board/seco/Kconfig
+
endif
diff --git a/board/seco/Kconfig b/board/seco/Kconfig
new file mode 100644
index 000..dcb1ac8
--- /dev/null
+++ b/board/seco/Kconfig
@@ -0,0 +1,63 @@
+if TARGET_SECOMX6
+
+choice
+ prompt SECO i.MX6 Board variant
+
+config SECOMX6_Q7
+ bool Q7
+
+config SECOMX6_UQ7
+ bool uQ7
+
+config SECOMX6_USBC
+ bool uSBC
+
+endchoice
+
+choice
+ prompt SECO i.MX6 SoC variant
+
+config SECOMX6Q
+ bool i.MX6Q
+ select MX6Q
+
+config SECOMX6DL
+ bool i.MX6DL
+ select MX6DL
+
+config SECOMX6S
+ bool i.MX6S
+ select MX6S
+
+endchoice
+
+choice
+ prompt DDR size
+
+config SECOMX6_512MB
+ bool 512MB
+
+config SECOMX6_1GB
+ bool 1GB
+
+config SECOMX6_2GB
+ bool 2GB
+
+config SECOMX6_4GB
+ bool 4GB
+
+endchoice
+
+config IMX_CONFIG
+ default board/seco/mx6quq7/mx6quq7-2g.cfg if SECOMX6_UQ7 SECOMX6Q
SECOMX6_2GB
+
+config SYS_BOARD
+ default mx6quq7 if SECOMX6_UQ7 SECOMX6Q
+
+config SYS_VENDOR
+ default seco
+
+config SYS_CONFIG_NAME
+ default secomx6quq7 if SECOMX6_UQ7 SECOMX6Q
+
+endif
diff --git a/board/seco/common/Makefile b/board/seco/common/Makefile
new file mode 100644
index 000..9e37ebb
--- /dev/null
+++ b/board/seco/common/Makefile
@@ -0,0 +1,2 @@
+
+obj-$(CONFIG_TARGET_SECOMX6) += mx6.o
diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c
new file mode 100644
index 000..2f14f59
--- /dev/null
+++ b/board/seco/common/mx6.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 ECA Sinters
+ *
+ * Author: Fabio Estevam fabio.este...@freescale.com
+ * Modified by: Boris Brezillon boris.brezil...@free-electrons.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/arch/clock.h
+#include asm/arch/imx-regs.h
+#include asm/arch/iomux.h
+#include asm/arch/mx6-pins.h
+#include asm/errno.h
+#include asm/gpio.h
+#include asm/imx-common/iomux-v3.h
+#include asm/imx-common/boot_mode.h
+#include mmc.h
+#include fsl_esdhc.h
+#include miiphy.h
+#include netdev.h
+#include asm/arch/mxc_hdmi.h
+#include asm/arch/crm_regs.h
+#include linux/fb.h
+#include ipu_pixfmt.h
+#include asm/io.h
+#include asm/arch/sys_proto.h
+#include micrel.h
+#include asm/imx-common/mxc_i2c.h
+#include i2c.h
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void seco_mx6_setup_uart_iomux(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+PAD_CTL_SPEED_MED |\
+PAD_CTL_DSE_40ohm |\
+PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC |
