Re: [U-Boot] [PATCH v2 4/4] malta: Allow MIPS64 builds

[Daniel Schwierzeck]

Am 26.05.2016 um 15:49 schrieb Paul Burton:
> Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
> support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
> which enables the user to make use of the whole 64 bit address space.
> 
> Signed-off-by: Paul Burton 
> ---
> 
> Changes in v2: None
> 
>  arch/mips/Kconfig  |  3 +++
>  board/imgtec/malta/Kconfig |  3 ++-
>  board/imgtec/malta/lowlevel_init.S | 13 +++--
>  include/configs/malta.h| 18 +-
>  4 files changed, 25 insertions(+), 12 deletions(-)
> 

applied to u-boot-mips, thanks.

-- 
- Daniel



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[U-Boot] [PATCH v2 4/4] malta: Allow MIPS64 builds

[Paul Burton]

Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton 
---

Changes in v2: None

 arch/mips/Kconfig  |  3 +++
 board/imgtec/malta/Kconfig |  3 ++-
 board/imgtec/malta/lowlevel_init.S | 13 +++--
 include/configs/malta.h| 18 +-
 4 files changed, 25 insertions(+), 12 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 53363e3..abaeaf0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -33,6 +33,9 @@ config TARGET_MALTA
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select SUPPORTS_CPU_MIPS32_R6
+   select SUPPORTS_CPU_MIPS64_R1
+   select SUPPORTS_CPU_MIPS64_R2
+   select SUPPORTS_CPU_MIPS64_R6
select SWAP_IO_SPACE
select MIPS_L1_CACHE_SHIFT_6
 
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 2bb8e8b..98eb4d1 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -10,6 +10,7 @@ config SYS_CONFIG_NAME
default "malta"
 
 config SYS_TEXT_BASE
-   default 0xbe00
+   default 0xbe00 if 32BIT
+   default 0xbe00 if 64BIT
 
 endif
diff --git a/board/imgtec/malta/lowlevel_init.S 
b/board/imgtec/malta/lowlevel_init.S
index 534db1d..3d48cdc 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -10,6 +10,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,7 +35,7 @@ lowlevel_init:
mtc0t0, CP0_CONFIG, 2
 
/* detect the core card */
-   li  t0, KSEG1ADDR(MALTA_REVISION)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_REVISION)
lw  t0, 0(t0)
srl t0, t0, MALTA_REVISION_CORID_SHF
andit0, t0, (MALTA_REVISION_CORID_MSK >> \
@@ -68,12 +69,12 @@ lowlevel_init:
 */
 _gt64120:
/* move GT64120 registers from 0x1400 to 0x1be0 */
-   li  t1, KSEG1ADDR(GT_DEF_BASE)
+   PTR_LI  t1, CKSEG1ADDR(GT_DEF_BASE)
li  t0, CPU_TO_GT32(0xdf00)
sw  t0, GT_ISD_OFS(t1)
 
/* setup MEM-to-PCI0 mapping */
-   li  t1, KSEG1ADDR(MALTA_GT_BASE)
+   PTR_LI  t1, CKSEG1ADDR(MALTA_GT_BASE)
 
/* setup PCI0 io window to 0x1800-0x181f */
li  t0, CPU_TO_GT32(0xc000)
@@ -100,7 +101,7 @@ _gt64120:
 */
 _msc01:
/* setup peripheral bus controller clock divide */
-   li  t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
li  t1, 0x1 << MSC01_PBC_CLKCFG_SHF
sw  t1, MSC01_PBC_CLKCFG_OFS(t0)
 
@@ -122,7 +123,7 @@ _msc01:
sw  t1, MSC01_PBC_CS0CFG_OFS(t0)
 
/* setup basic address decode */
-   li  t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li  t1, 0x0
li  t2, -CONFIG_SYS_MEM_SIZE
sw  t1, MSC01_BIU_MCBAS1L_OFS(t0)
@@ -157,7 +158,7 @@ _msc01:
sw  t2, MSC01_BIU_IP3MSK2L_OFS(t0)
 
/* setup PCI memory */
-   li  t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+   PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
li  t1, MALTA_MSC01_PCIMEM_BASE
li  t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
li  t3, MALTA_MSC01_PCIMEM_MAP
diff --git a/include/configs/malta.h b/include/configs/malta.h
index a369678..fc4baba 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -39,14 +39,18 @@
  */
 #define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_SDRAM_BASE  0x8000 /* Cached addr */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE 0x8000
+#else
+# define CONFIG_SYS_SDRAM_BASE 0x8000
+#endif
 #define CONFIG_SYS_MEM_SIZE(256 * 1024 * 1024)
 
 #define CONFIG_SYS_INIT_SP_OFFSET  0x40
 
-#define CONFIG_SYS_LOAD_ADDR   0x8100
-#define CONFIG_SYS_MEMTEST_START   0x8010
-#define CONFIG_SYS_MEMTEST_END 0x8080
+#define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_SDRAM_BASE + 0x0100)
+#define CONFIG_SYS_MEMTEST_START   (CONFIG_SYS_SDRAM_BASE + 0x0010)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x0080)
 
 #define CONFIG_SYS_MALLOC_LEN  (128 * 1024)
 #define CONFIG_SYS_BOOTPARAMS_LEN  (128 * 1024)
@@ -69,7 +73,11 @@
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_FLASH_BASE  0xbe00
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_FLASH_BASE 0xbe00
+#else
+# define CONFIG_SYS_FLASH_BASE 0xbe00
+#endif
 #define CONFIG_SYS_MAX_FLASH_BANKS 1
 #define CONFIG_SYS_MAX_FLASH_SECT  128
 #define CONFIG_SYS_FLASH_CFI
-- 
2.8.3