Re: [U-Boot] [PATCH v3] arm: ls1021a: Add sata support on qds and twr board

2015-10-30 Thread York Sun 


On 10/16/2015 01:06 AM, Tang Yuantian wrote:
> Freescale ARM-based Layerscape LS102xA contain a SATA controller
> which comply with the serial ATA 3.0 specification and the
> AHCI 1.3 specification.
> This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
> 
> Signed-off-by: Tang Yuantian 
> ---
> v3:
>   - refactor the framework
>   - replace hard coding with MICRO
> v2:
>   - rebase to latest git tree
>   - use micro SATA_ECC_REG_ADDR instead of hard coding 


Applied to u-boot-fsl-qoriq. Awaiting upstream. Thanks.

York

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[U-Boot] [PATCH v3] arm: ls1021a: Add sata support on qds and twr board

2015-10-16 Thread Tang Yuantian 
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian 
---
v3:
- refactor the framework
- replace hard coding with MICRO
v2:
- rebase to latest git tree
- use micro SATA_ECC_REG_ADDR instead of hard coding 

 arch/arm/cpu/armv7/ls102xa/Makefile   |  1 +
 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 42 +++
 arch/arm/include/asm/arch-ls102xa/config.h| 15 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +
 arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h  | 11 ++
 board/freescale/ls1021aqds/ls1021aqds.c   | 12 +++
 board/freescale/ls1021atwr/ls1021atwr.c   | 12 +++
 7 files changed, 117 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile 
b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2d55782..2311468 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -9,6 +9,7 @@ obj-y   += clock.o
 obj-y  += timer.o
 obj-y  += fsl_epu.o
 
+obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c 
b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
new file mode 100644
index 000..deeb674
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* port register default value */
+#define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY_2_CFG0x28183411
+#define AHCI_PORT_PHY_3_CFG0x0e081004
+#define AHCI_PORT_PHY_4_CFG0x00480811
+#define AHCI_PORT_PHY_5_CFG0x192c96a4
+#define AHCI_PORT_TRANS_CFG0x0825
+
+#define SATA_ECC_REG_ADDR  0x20220520
+#define SATA_ECC_DISABLE   0x0002
+
+int ls1021a_sata_init(void)
+{
+   struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+   out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
+
+   out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+   out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+   out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+   out_le32(_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
+   out_le32(_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
+   out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+   ahci_init((void __iomem *)AHCI_BASE_ADDR);
+   scsi_scan(0);
+
+   return 0;
+}
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h 
b/arch/arm/include/asm/arch-ls102xa/config.h
index bcaf7bf..f066480 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,6 +79,21 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
 CONFIG_SYS_PCIE2_VIRT_ADDR)
 
+/* SATA */
+#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x0220)
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+   CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_ERRATUM_A008407
+
 #ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_FSL_DDR_BE
 #define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 60aa0d3..5e49703 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -397,4 +397,28 @@ struct ccsr_cci400 {
u8 res_e004[0x1 - 0xe004];
 };
 
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+   u32 res1[0xa4/4];   /* 0x0 - 0xa4 */
+   u32 pcfg;   /* port config */
+   u32 ppcfg;  /* port phy1 config */
+   u32 pp2c;   /* port phy2 config */
+   u32 pp3c;   /* port phy3 config */
+   u32 pp4c;   /* port phy4 config */
+   u32 pp5c;   /* port phy5 config */
+   u32 paxic;  /* port AXI config */
+   u32 axicc;  /* AXI cache control */
+   u32 axipc;  /* AXI PROT control */
+   u32 ptc;/* port Trans Config */
+   u32 pts;/* port Trans Status */
+   u32 plc;/*