This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
Instead of supporting both HW revisions of the controller in a single build,
support has been split by the selected config to save space.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v3: rename BCM6338 SPI driver to BCM6348
switch to devfdt_get_addr_size_index()
v2: no changes
drivers/spi/Kconfig | 21 +++
drivers/spi/Makefile | 1 +
drivers/spi/bcm63xx_spi.c | 404 ++
3 files changed, 426 insertions(+)
create mode 100644 drivers/spi/bcm63xx_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bef864f..0b408db 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -40,6 +40,27 @@ config ATMEL_SPI
many AT32 (AVR32) and AT91 (ARM) chips. This driver can be
used to access the SPI Flash, such as AT25DF321.
+choice
+ prompt "BCM63xx SPI driver"
+ depends on ARCH_BMIPS
+ optional
+
+config BCM6348_SPI
+ bool "BCM6348 SPI driver"
+ help
+ Enable the BCM6348 SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Broadcom
+ SPI core.
+
+config BCM6358_SPI
+ bool "BCM6358 SPI driver"
+ help
+ Enable the BCM6358 SPI driver. This driver can be used to
+ access the SPI NOR flash on platforms embedding this Broadcom
+ SPI core.
+
+endchoice
+
config CADENCE_QSPI
bool "Cadence QSPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c090562..2795a34 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+obj-$(CONFIG_BCM6348_SPI)$(CONFIG_BCM6358_SPI) += bcm63xx_spi.o
obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
new file mode 100644
index 000..d3aad70
--- /dev/null
+++ b/drivers/spi/bcm63xx_spi.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas
+ *
+ * Derived from linux/drivers/spi/spi-bcm63xx.c:
+ * Copyright (C) 2009-2012 Florian Fainelli
+ * Copyright (C) 2010 Tanguy Bouzeloc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_BCM6348_SPI)
+
+# define SPI_DT_ID "brcm,bcm6348-spi"
+
+/* SPI Command register */
+# define SPI_CMD_REG 0x00
+
+/* SPI Interrupt registers */
+# define SPI_IR_STAT_REG 0x02
+# define SPI_IR_MASK_REG 0x04
+
+/* SPI Clock register */
+# define SPI_CLK_REG 0x06
+
+/* SPI Fill register */
+# define SPI_FILL_REG 0x07
+
+/* SPI Control register (8 bit) */
+# define SPI_CTL_REG 0x40
+# define SPI_CTL_BYTES_SHIFT 0
+# define SPI_CTL_BYTES_MASK(0x3f << SPI_CTL_BYTES_SHIFT)
+# define SPI_CTL_TYPE_SHIFT6
+# define SPI_CTL_TYPE_FD_RW(0 << SPI_CTL_TYPE_SHIFT)
+# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT)
+# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)
+
+# define bcm63xx_spi_wctl(v,a) writeb_be(v, a);
+
+/* SPI TX Data registers */
+# define SPI_TX_DATA_REG 0x41
+# define SPI_TX_DATA_SIZE 0x3f
+
+/* SPI RX Data registers */
+# define SPI_RX_DATA_REG 0x80
+# define SPI_RX_DATA_SIZE 0x3f
+
+#elif defined(CONFIG_BCM6358_SPI)
+
+# define SPI_DT_ID "brcm,bcm6358-spi"
+
+/* SPI Control register (16 bit) */
+# define SPI_CTL_REG 0x000
+# define SPI_CTL_BYTES_SHIFT 0
+# define SPI_CTL_BYTES_MASK(0x3ff << SPI_CTL_BYTES_SHIFT)
+# define SPI_CTL_TYPE_SHIFT14
+# define SPI_CTL_TYPE_FD_RW(0 << SPI_CTL_TYPE_SHIFT)
+# define SPI_CTL_TYPE_HD_W (1 << SPI_CTL_TYPE_SHIFT)
+# define SPI_CTL_TYPE_HD_R (2 << SPI_CTL_TYPE_SHIFT)
+
+# define bcm63xx_spi_wctl(v,a) writew_be(v, a);
+
+/* SPI TX Data registers */
+# define SPI_TX_DATA_REG 0x002
+# define SPI_TX_DATA_SIZE 0x21e
+
+/* SPI RX Data registers */
+# define SPI_RX_DATA_REG 0x400
+# define SPI_RX_DATA_SIZE 0x220
+
+/* SPI Command register */
+# define SPI_CMD_REG 0x700
+
+/* SPI Interrupt registers */
+# define SPI_IR_STAT_REG 0x702
+# define SPI_IR_MASK_REG 0x704
+
+/* SPI Clock register */
+# define SPI_CLK_REG 0x706
+
+/* SPI Fill register */
+# define SPI_FILL_REG 0x707
+
+#endif
+
+/* SPI Command register */
+#define SPI_CMD_OP_SHIFT 0
+#define SPI_CMD_OP_START (0x3 << SPI_CMD_OP_SHIFT)
+#define SPI_CMD_SLAVE_SHIFT4
+#define SPI_CMD_SLAVE_MASK