Re: [U-Boot] [PATCH v3 03/10] pinctrl: rockchip: Split the common set_mux() into per Soc【请注意，邮件由u-boot-boun...@lists.denx.de代发】
On 05/07/2019 11:43 AM, Kever Yang wrote:
>
> On 04/16/2019 09:50 PM, David Wu wrote:
>> Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
>> higher 16 writing corresponding bits, use common set_mux() func would
>> introduce more code, so implement their set_mux() in each Soc's own
>> file to reduce the size of code.
>>
>> Signed-off-by: David Wu
> Reviewed-by: Kever Yang
Applied to u-boot-rockchip, thanks!
>
> Thanks,
> - Kever
>> ---
>>
>> Change in v3:
>> - None
>>
>> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 25 +++
>> drivers/pinctrl/rockchip/pinctrl-rk3128.c | 37 +
>> drivers/pinctrl/rockchip/pinctrl-rk3188.c | 25 +++
>> drivers/pinctrl/rockchip/pinctrl-rk322x.c | 34 +++
>> drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +++-
>> drivers/pinctrl/rockchip/pinctrl-rk3328.c | 37 +
>> drivers/pinctrl/rockchip/pinctrl-rk3368.c | 25 +++
>> drivers/pinctrl/rockchip/pinctrl-rk3399.c | 34 +++
>> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 41 +--
>> drivers/pinctrl/rockchip/pinctrl-rockchip.h | 8
>> drivers/pinctrl/rockchip/pinctrl-rv1108.c | 28 +
>> 11 files changed, 297 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> index 2a651cd9b8..8969aea2e3 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
>> @@ -11,6 +11,30 @@
>>
>> #include "pinctrl-rockchip.h"
>>
>> +static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> +struct rockchip_pinctrl_priv *priv = bank->priv;
>> +int iomux_num = (pin / 8);
>> +struct regmap *regmap;
>> +int reg, ret, mask, mux_type;
>> +u8 bit;
>> +u32 data;
>> +
>> +regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> +? priv->regmap_pmu : priv->regmap_base;
>> +
>> +/* get basic quadrupel of mux registers and the correct reg inside */
>> +mux_type = bank->iomux[iomux_num].type;
>> +reg = bank->iomux[iomux_num].offset;
>> +reg += rockchip_get_mux_data(mux_type, pin, , );
>> +
>> +data = (mask << (bit + 16));
>> +data |= (mux & mask) << bit;
>> +ret = regmap_write(regmap, reg, data);
>> +
>> +return ret;
>> +}
>> +
>> #define RK3036_PULL_OFFSET 0x118
>> #define RK3036_PULL_PINS_PER_REG16
>> #define RK3036_PULL_BANK_STRIDE 8
>> @@ -41,6 +65,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
>> .label = "RK3036-GPIO",
>> .type = RK3036,
>> .grf_mux_offset = 0xa8,
>> +.set_mux= rk3036_set_mux,
>> .pull_calc_reg = rk3036_calc_pull_reg_and_bit,
>> };
>>
>> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> index 43a6c173a0..de203334c7 100644
>> --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
>> @@ -98,6 +98,42 @@ static struct rockchip_mux_route_data
>> rk3128_mux_route_data[] = {
>> },
>> };
>>
>> +static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
>> +{
>> +struct rockchip_pinctrl_priv *priv = bank->priv;
>> +int iomux_num = (pin / 8);
>> +struct regmap *regmap;
>> +int reg, ret, mask, mux_type;
>> +u8 bit;
>> +u32 data, route_reg, route_val;
>> +
>> +regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> +? priv->regmap_pmu : priv->regmap_base;
>> +
>> +/* get basic quadrupel of mux registers and the correct reg inside */
>> +mux_type = bank->iomux[iomux_num].type;
>> +reg = bank->iomux[iomux_num].offset;
>> +reg += rockchip_get_mux_data(mux_type, pin, , );
>> +
>> +if (bank->recalced_mask & BIT(pin))
>> +rockchip_get_recalced_mux(bank, pin, , , );
>> +
>> +if (bank->route_mask & BIT(pin)) {
>> +if (rockchip_get_mux_route(bank, pin, mux, _reg,
>> + _val)) {
>> +ret = regmap_write(regmap, route_reg, route_val);
>> +if (ret)
>> +return ret;
>> +}
>> +}
>> +
>> +data = (mask << (bit + 16));
>> +data |= (mux & mask) << bit;
>> +ret = regmap_write(regmap, reg, data);
>> +
>> +return ret;
>> +}
>> +
>> #define RK3128_PULL_OFFSET 0x118
>> #define RK3128_PULL_PINS_PER_REG16
>> #define RK3128_PULL_BANK_STRIDE 8
>> @@ -133,6 +169,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
>> .niomux_recalced= ARRAY_SIZE(rk3128_mux_recalced_data),
>> .iomux_routes = rk3128_mux_route_data,
>> .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
>>
Re: [U-Boot] [PATCH v3 03/10] pinctrl: rockchip: Split the common set_mux() into per Soc
On 04/16/2019 09:50 PM, David Wu wrote:
> Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
> higher 16 writing corresponding bits, use common set_mux() func would
> introduce more code, so implement their set_mux() in each Soc's own
> file to reduce the size of code.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
> ---
>
> Change in v3:
> - None
>
> drivers/pinctrl/rockchip/pinctrl-rk3036.c | 25 +++
> drivers/pinctrl/rockchip/pinctrl-rk3128.c | 37 +
> drivers/pinctrl/rockchip/pinctrl-rk3188.c | 25 +++
> drivers/pinctrl/rockchip/pinctrl-rk322x.c | 34 +++
> drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +++-
> drivers/pinctrl/rockchip/pinctrl-rk3328.c | 37 +
> drivers/pinctrl/rockchip/pinctrl-rk3368.c | 25 +++
> drivers/pinctrl/rockchip/pinctrl-rk3399.c | 34 +++
> .../pinctrl/rockchip/pinctrl-rockchip-core.c | 41 +--
> drivers/pinctrl/rockchip/pinctrl-rockchip.h | 8
> drivers/pinctrl/rockchip/pinctrl-rv1108.c | 28 +
> 11 files changed, 297 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
> b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
> index 2a651cd9b8..8969aea2e3 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
> @@ -11,6 +11,30 @@
>
> #include "pinctrl-rockchip.h"
>
> +static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask, mux_type;
> + u8 bit;
> + u32 data;
> +
> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + ? priv->regmap_pmu : priv->regmap_base;
> +
> + /* get basic quadrupel of mux registers and the correct reg inside */
> + mux_type = bank->iomux[iomux_num].type;
> + reg = bank->iomux[iomux_num].offset;
> + reg += rockchip_get_mux_data(mux_type, pin, , );
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> #define RK3036_PULL_OFFSET 0x118
> #define RK3036_PULL_PINS_PER_REG 16
> #define RK3036_PULL_BANK_STRIDE 8
> @@ -41,6 +65,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
> .label = "RK3036-GPIO",
> .type = RK3036,
> .grf_mux_offset = 0xa8,
> + .set_mux= rk3036_set_mux,
> .pull_calc_reg = rk3036_calc_pull_reg_and_bit,
> };
>
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
> b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
> index 43a6c173a0..de203334c7 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
> @@ -98,6 +98,42 @@ static struct rockchip_mux_route_data
> rk3128_mux_route_data[] = {
> },
> };
>
> +static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask, mux_type;
> + u8 bit;
> + u32 data, route_reg, route_val;
> +
> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + ? priv->regmap_pmu : priv->regmap_base;
> +
> + /* get basic quadrupel of mux registers and the correct reg inside */
> + mux_type = bank->iomux[iomux_num].type;
> + reg = bank->iomux[iomux_num].offset;
> + reg += rockchip_get_mux_data(mux_type, pin, , );
> +
> + if (bank->recalced_mask & BIT(pin))
> + rockchip_get_recalced_mux(bank, pin, , , );
> +
> + if (bank->route_mask & BIT(pin)) {
> + if (rockchip_get_mux_route(bank, pin, mux, _reg,
> +_val)) {
> + ret = regmap_write(regmap, route_reg, route_val);
> + if (ret)
> + return ret;
> + }
> + }
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> #define RK3128_PULL_OFFSET 0x118
> #define RK3128_PULL_PINS_PER_REG 16
> #define RK3128_PULL_BANK_STRIDE 8
> @@ -133,6 +169,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
> .niomux_recalced= ARRAY_SIZE(rk3128_mux_recalced_data),
> .iomux_routes = rk3128_mux_route_data,
> .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
> + .set_mux= rk3128_set_mux,
> .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
> };
>
> diff --git
[U-Boot] [PATCH v3 03/10] pinctrl: rockchip: Split the common set_mux() into per Soc
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu
---
Change in v3:
- None
drivers/pinctrl/rockchip/pinctrl-rk3036.c | 25 +++
drivers/pinctrl/rockchip/pinctrl-rk3128.c | 37 +
drivers/pinctrl/rockchip/pinctrl-rk3188.c | 25 +++
drivers/pinctrl/rockchip/pinctrl-rk322x.c | 34 +++
drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +++-
drivers/pinctrl/rockchip/pinctrl-rk3328.c | 37 +
drivers/pinctrl/rockchip/pinctrl-rk3368.c | 25 +++
drivers/pinctrl/rockchip/pinctrl-rk3399.c | 34 +++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 41 +--
drivers/pinctrl/rockchip/pinctrl-rockchip.h | 8
drivers/pinctrl/rockchip/pinctrl-rv1108.c | 28 +
11 files changed, 297 insertions(+), 32 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
index 2a651cd9b8..8969aea2e3 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c
@@ -11,6 +11,30 @@
#include "pinctrl-rockchip.h"
+static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, , );
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3036_PULL_OFFSET 0x118
#define RK3036_PULL_PINS_PER_REG 16
#define RK3036_PULL_BANK_STRIDE8
@@ -41,6 +65,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.label = "RK3036-GPIO",
.type = RK3036,
.grf_mux_offset = 0xa8,
+ .set_mux= rk3036_set_mux,
.pull_calc_reg = rk3036_calc_pull_reg_and_bit,
};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
index 43a6c173a0..de203334c7 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c
@@ -98,6 +98,42 @@ static struct rockchip_mux_route_data
rk3128_mux_route_data[] = {
},
};
+static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data, route_reg, route_val;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ reg += rockchip_get_mux_data(mux_type, pin, , );
+
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, , , );
+
+ if (bank->route_mask & BIT(pin)) {
+ if (rockchip_get_mux_route(bank, pin, mux, _reg,
+ _val)) {
+ ret = regmap_write(regmap, route_reg, route_val);
+ if (ret)
+ return ret;
+ }
+ }
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
#define RK3128_PULL_OFFSET 0x118
#define RK3128_PULL_PINS_PER_REG 16
#define RK3128_PULL_BANK_STRIDE8
@@ -133,6 +169,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.niomux_recalced= ARRAY_SIZE(rk3128_mux_recalced_data),
.iomux_routes = rk3128_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
+ .set_mux= rk3128_set_mux,
.pull_calc_reg = rk3128_calc_pull_reg_and_bit,
};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c
b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
index 7cc52c0075..617ae28ac8 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c
@@ -11,6
